{"id":"https://openalex.org/W2085331651","doi":"https://doi.org/10.1109/tvlsi.2015.2397449","title":"A Cellular Network Architecture With Polynomial Weight Functions","display_name":"A Cellular Network Architecture With Polynomial Weight Functions","publication_year":2015,"publication_date":"2015-02-12","ids":{"openalex":"https://openalex.org/W2085331651","doi":"https://doi.org/10.1109/tvlsi.2015.2397449","mag":"2085331651"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2397449","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2397449","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101617193","display_name":"Jens M\u00fcller","orcid":"https://orcid.org/0000-0001-9875-3534"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jens Muller","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033951881","display_name":"Jan M\u00fcller","orcid":"https://orcid.org/0000-0001-8085-4599"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jan Muller","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022074775","display_name":"Robert Braunschweig","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Robert Braunschweig","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012451668","display_name":"Ronald Tetzlaff","orcid":"https://orcid.org/0000-0001-7436-0103"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ronald Tetzlaff","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":1.0155,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.79971147,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"24","issue":"1","first_page":"353","last_page":"357"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11347","display_name":"Neural Networks Stability and Synchronization","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11347","display_name":"Neural Networks Stability and Synchronization","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9710000157356262,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9302999973297119,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6806796789169312},{"id":"https://openalex.org/keywords/polynomial","display_name":"Polynomial","score":0.5957040786743164},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5904918909072876},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5372104644775391},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.522439181804657},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47668933868408203},{"id":"https://openalex.org/keywords/finite-field","display_name":"Finite field","score":0.4438633620738983},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.4427621364593506},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.4233439564704895},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.40859246253967285},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.38144928216934204},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.37694695591926575},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3651946783065796},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32526618242263794},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3009249269962311},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23327317833900452},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.1368844211101532}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6806796789169312},{"id":"https://openalex.org/C90119067","wikidata":"https://www.wikidata.org/wiki/Q43260","display_name":"Polynomial","level":2,"score":0.5957040786743164},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5904918909072876},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5372104644775391},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.522439181804657},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47668933868408203},{"id":"https://openalex.org/C77926391","wikidata":"https://www.wikidata.org/wiki/Q603880","display_name":"Finite field","level":2,"score":0.4438633620738983},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.4427621364593506},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4233439564704895},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.40859246253967285},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.38144928216934204},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.37694695591926575},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3651946783065796},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32526618242263794},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3009249269962311},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23327317833900452},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.1368844211101532},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2015.2397449","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2397449","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1825194443","https://openalex.org/W1969052504","https://openalex.org/W1978825047","https://openalex.org/W2019849627","https://openalex.org/W2027436051","https://openalex.org/W2052773149","https://openalex.org/W2072497408","https://openalex.org/W2090192869","https://openalex.org/W2093606673","https://openalex.org/W2098870573","https://openalex.org/W2108548330","https://openalex.org/W2117148079","https://openalex.org/W2118964038","https://openalex.org/W2120283686","https://openalex.org/W2130416988","https://openalex.org/W2132085403","https://openalex.org/W2160121923","https://openalex.org/W2161331734","https://openalex.org/W2167267517","https://openalex.org/W4251292953","https://openalex.org/W6679606916"],"related_works":["https://openalex.org/W1876592433","https://openalex.org/W2083269738","https://openalex.org/W4210376836","https://openalex.org/W4210925376","https://openalex.org/W1633995705","https://openalex.org/W2596211269","https://openalex.org/W197862639","https://openalex.org/W2360384790","https://openalex.org/W4232397253","https://openalex.org/W4235913033"],"abstract_inverted_index":{"Emulations":[0],"of":[1,15,23,46,58,69,77],"cellular":[2],"nonlinear":[3],"networks":[4,72],"on":[5,80],"digital":[6,30],"reconfigurable":[7],"hardware":[8],"are":[9],"renowned":[10],"for":[11,39],"an":[12,64],"efficient":[13],"computation":[14],"massive":[16],"data,":[17],"exceeding":[18],"the":[19,40,50,56],"accuracy":[20],"and":[21,54],"flexibility":[22],"full-custom":[24],"designs.":[25],"In":[26],"this":[27],"contribution,":[28],"a":[29,74],"implementation":[31],"with":[32,73],"polynomial":[33],"coupling":[34],"weight":[35],"functions":[36],"is":[37,67],"proposed":[38],"first":[41],"time,":[42],"establishing":[43],"novel":[44],"fields":[45],"application,":[47],"e.g.,":[48],"in":[49,55],"medical":[51],"signal":[52],"processing":[53,70],"solution":[57],"partial":[59],"differential":[60],"equations.":[61],"We":[62],"present":[63],"architecture":[65],"that":[66],"capable":[68],"large-scale":[71],"high":[75],"degree":[76],"parallelism,":[78],"implemented":[79],"state-of-the-art":[81],"field-programmable":[82],"gate":[83],"arrays.":[84]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
