{"id":"https://openalex.org/W1963818365","doi":"https://doi.org/10.1109/tvlsi.2015.2393914","title":"An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating","display_name":"An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating","publication_year":2015,"publication_date":"2015-02-12","ids":{"openalex":"https://openalex.org/W1963818365","doi":"https://doi.org/10.1109/tvlsi.2015.2393914","mag":"1963818365"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2393914","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2393914","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016242113","display_name":"Assem A. M. Bsoul","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Assem A. M. Bsoul","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada","Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J. E. Wilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada","Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009397115","display_name":"Kuen Hung Tsoi","orcid":"https://orcid.org/0000-0002-6856-6727"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Kuen Hung Tsoi","raw_affiliation_strings":["Department of Computing, Imperial College London, London, U.K","Department of Computing, Imperial College London, London, U.K.#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computing, Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Computing, Imperial College London, London, U.K.#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057940557","display_name":"Wayne Luk","orcid":"https://orcid.org/0000-0002-6750-927X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Department of Computing, Imperial College London, London, U.K","Department of Computing, Imperial College London, London, U.K.#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computing, Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Computing, Imperial College London, London, U.K.#TAB#","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3605,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.82947184,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"24","issue":"1","first_page":"178","last_page":"191"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.859123945236206},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7909625768661499},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7015258073806763},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6053623557090759},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5653432607650757},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4481036067008972},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4419742822647095},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.43773502111434937},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.411914587020874},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4059023857116699},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.34764936566352844},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3094421625137329},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.3063434362411499},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15816113352775574},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1404045820236206},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.12802061438560486},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.08976632356643677}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.859123945236206},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7909625768661499},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7015258073806763},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6053623557090759},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5653432607650757},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4481036067008972},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4419742822647095},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.43773502111434937},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.411914587020874},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4059023857116699},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.34764936566352844},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3094421625137329},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3063434362411499},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15816113352775574},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1404045820236206},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.12802061438560486},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.08976632356643677},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2015.2393914","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2393914","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:spiral.imperial.ac.uk:10044/1/23837","is_oa":false,"landing_page_url":"http://hdl.handle.net/10044/1/23837","pdf_url":null,"source":{"id":"https://openalex.org/S4306401396","display_name":"Spiral (Imperial College London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I47508984","host_organization_name":"Imperial College London","host_organization_lineage":["https://openalex.org/I47508984"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"191","raw_type":"Journal Article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6700000166893005,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G4739172974","display_name":null,"funder_award_id":"318521","funder_id":"https://openalex.org/F4320333065","funder_display_name":"Seventh Framework Programme"},{"id":"https://openalex.org/G6367779196","display_name":null,"funder_award_id":"EP/I012036/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G7124963838","display_name":null,"funder_award_id":"287804","funder_id":"https://openalex.org/F4320333065","funder_display_name":"Seventh Framework Programme"},{"id":"https://openalex.org/G8704836312","display_name":null,"funder_award_id":"257906","funder_id":"https://openalex.org/F4320333065","funder_display_name":"Seventh Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320333065","display_name":"Seventh Framework Programme","ror":null},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W152265269","https://openalex.org/W152792319","https://openalex.org/W653285986","https://openalex.org/W1518236483","https://openalex.org/W1523051745","https://openalex.org/W1582019256","https://openalex.org/W1943183861","https://openalex.org/W1984981318","https://openalex.org/W1994298038","https://openalex.org/W2001824086","https://openalex.org/W2008852833","https://openalex.org/W2023900486","https://openalex.org/W2035847677","https://openalex.org/W2036205274","https://openalex.org/W2041557219","https://openalex.org/W2077117260","https://openalex.org/W2094806828","https://openalex.org/W2115402073","https://openalex.org/W2123400059","https://openalex.org/W2123491437","https://openalex.org/W2125788370","https://openalex.org/W2128677987","https://openalex.org/W2133712953","https://openalex.org/W2137128428","https://openalex.org/W2137769675","https://openalex.org/W2137978438","https://openalex.org/W2138840350","https://openalex.org/W2141519923","https://openalex.org/W2151731855","https://openalex.org/W2168493238","https://openalex.org/W3139852744","https://openalex.org/W4230451466","https://openalex.org/W4249083156","https://openalex.org/W6606218650"],"related_works":["https://openalex.org/W2152979262","https://openalex.org/W3127845477","https://openalex.org/W2485892467","https://openalex.org/W4252084893","https://openalex.org/W1949070338","https://openalex.org/W2938543345","https://openalex.org/W4390197045","https://openalex.org/W1510566755","https://openalex.org/W2102121056","https://openalex.org/W2003272148"],"abstract_inverted_index":{"Leakage":[0],"power":[1,9,68,119,129],"is":[2,136,175],"an":[3,61],"important":[4],"component":[5],"of":[6,49,142,156,171],"the":[7,32,47,111,116,123,151,180],"total":[8],"consumption":[10],"in":[11,70,177,188,194],"field-programmable":[12],"gate":[13],"arrays":[14],"(FPGAs)":[15],"built":[16],"using":[17],"90-nm":[18],"and":[19,118,128],"smaller":[20],"technology":[21],"nodes.":[22],"Power":[23,154],"gating":[24,130,186],"was":[25],"shown":[26],"to":[27,84,107,110,138,150,158,190],"be":[28,75,105],"effective":[29],"at":[30,44,79],"reducing":[31],"leakage":[33],"power.":[34],"Previous":[35],"techniques":[36],"focus":[37],"on":[38,53],"turning":[39],"OFF":[40],"unused":[41],"FPGA":[42,62,72,125],"resources":[43,73],"configuration":[45],"time;":[46],"benefit":[48],"this":[50,57,195],"approach":[51],"depends":[52],"resource":[54],"utilization.":[55],"In":[56],"paper,":[58],"we":[59,166],"present":[60,99],"architecture":[63,126,182],"that":[64,103,145,174],"enables":[65],"dynamically":[66],"controlled":[67],"gating,":[69],"which":[71],"can":[74,104],"selectively":[76],"powered":[77],"down":[78],"run-time.":[80],"This":[81],"could":[82],"lead":[83],"significant":[85],"overall":[86],"energy":[87,192],"savings":[88,155,193],"for":[89,162],"applications":[90,109],"having":[91],"modules":[92,149],"with":[93,184],"long":[94],"idle":[95],"times.":[96],"We":[97,114],"also":[98],"a":[100,140,168,172],"CAD":[101,134],"flow":[102,135],"used":[106,137,176],"map":[108,139],"proposed":[112,133,152,181],"architecture.":[113,153],"study":[115,167],"area":[117],"tradeoffs":[120],"by":[121],"varying":[122],"different":[124],"parameters":[127],"granularity.":[131],"The":[132],"set":[141],"benchmark":[143],"circuits":[144],"have":[146],"multiple":[147],"power-gated":[148],"up":[157,189],"83%":[159],"are":[160],"achievable":[161],"these":[163],"circuits.":[164],"Finally,":[165],"control":[169],"system":[170],"robot":[173],"endoscopy.":[178],"Using":[179],"combined":[183],"clock":[185],"results":[187],"19%":[191],"application.":[196]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}