{"id":"https://openalex.org/W2163728097","doi":"https://doi.org/10.1109/tvlsi.2015.2388783","title":"Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques","display_name":"Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques","publication_year":2015,"publication_date":"2015-01-26","ids":{"openalex":"https://openalex.org/W2163728097","doi":"https://doi.org/10.1109/tvlsi.2015.2388783","mag":"2163728097"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2015.2388783","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2388783","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025694711","display_name":"Mingzhong Li","orcid":"https://orcid.org/0000-0002-9532-9049"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Ming-Zhong Li","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI and the Biomedical Engineering Laboratory, University of Macau, Macau, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI and the Biomedical Engineering Laboratory, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060389034","display_name":"Chio-In Ieong","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Chio-In Ieong","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI and the Biomedical Engineering Laboratory, University of Macau, Macau, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI and the Biomedical Engineering Laboratory, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029369208","display_name":"Man\u2010Kay Law","orcid":"https://orcid.org/0000-0002-2799-1129"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Man-Kay Law","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058845450","display_name":"Pui\u2010In Mak","orcid":"https://orcid.org/0000-0002-3579-8740"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Pui-In Mak","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037922594","display_name":"Mang I Vai","orcid":"https://orcid.org/0000-0003-0663-0049"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Mang-I Vai","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI and the Biomedical Engineering Laboratory, University of Macau, Macau, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI and the Biomedical Engineering Laboratory, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048442222","display_name":"Sio Hang Pun","orcid":"https://orcid.org/0000-0002-8648-2092"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Sio-Hang Pun","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI and the Biomedical Engineering Laboratory, University of Macau, Macau, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI and the Biomedical Engineering Laboratory, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal","institution_ids":["https://openalex.org/I203847022","https://openalex.org/I141596103"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.6372,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.83069095,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"23","issue":"12","first_page":"3119","last_page":"3123"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.7770029306411743},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7320736646652222},{"id":"https://openalex.org/keywords/inverse","display_name":"Inverse","score":0.5915216207504272},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5712824463844299},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47521382570266724},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4520823359489441},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.42134395241737366},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3853457570075989},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24557551741600037},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.23912525177001953},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.23675811290740967},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23551476001739502},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21045270562171936},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18576017022132874},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1273472011089325}],"concepts":[{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.7770029306411743},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7320736646652222},{"id":"https://openalex.org/C207467116","wikidata":"https://www.wikidata.org/wiki/Q4385666","display_name":"Inverse","level":2,"score":0.5915216207504272},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5712824463844299},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47521382570266724},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4520823359489441},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.42134395241737366},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3853457570075989},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24557551741600037},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.23912525177001953},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.23675811290740967},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23551476001739502},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21045270562171936},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18576017022132874},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1273472011089325},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2015.2388783","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2015.2388783","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G3692685927","display_name":null,"funder_award_id":"015/2012/A1","funder_id":"https://openalex.org/F4320323893","funder_display_name":"Fundo para o Desenvolvimento das Ci\u00eancias e da Tecnologia"},{"id":"https://openalex.org/G492912525","display_name":null,"funder_award_id":"047/2013/A2","funder_id":"https://openalex.org/F4320323893","funder_display_name":"Fundo para o Desenvolvimento das Ci\u00eancias e da Tecnologia"},{"id":"https://openalex.org/G7071897495","display_name":null,"funder_award_id":"024/2009/A1","funder_id":"https://openalex.org/F4320323893","funder_display_name":"Fundo para o Desenvolvimento das Ci\u00eancias e da Tecnologia"}],"funders":[{"id":"https://openalex.org/F4320323893","display_name":"Fundo para o Desenvolvimento das Ci\u00eancias e da Tecnologia","ror":"https://ror.org/05vna4324"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1966879182","https://openalex.org/W1975918566","https://openalex.org/W1997782294","https://openalex.org/W2025012216","https://openalex.org/W2031474029","https://openalex.org/W2034182926","https://openalex.org/W2035902393","https://openalex.org/W2053774923","https://openalex.org/W2062071853","https://openalex.org/W2076654948","https://openalex.org/W2079952652","https://openalex.org/W2087107264","https://openalex.org/W2088115909","https://openalex.org/W2097579177","https://openalex.org/W2107103004","https://openalex.org/W2140863609","https://openalex.org/W2150564053","https://openalex.org/W2156638740","https://openalex.org/W4230854430","https://openalex.org/W4254883677","https://openalex.org/W6669880274"],"related_works":["https://openalex.org/W2171305391","https://openalex.org/W2168517613","https://openalex.org/W2123241142","https://openalex.org/W2324812725","https://openalex.org/W2947747257","https://openalex.org/W1973928325","https://openalex.org/W2163728097","https://openalex.org/W2006886358","https://openalex.org/W2741523884","https://openalex.org/W2546070325"],"abstract_inverted_index":{"Ultralow-energy":[0],"biomedical":[1],"applications":[2],"have":[3],"urged":[4],"the":[5,31,35,49,77,113,120,123],"development":[6],"of":[7,34,51,94,122],"a":[8,92],"subthreshold":[9],"VLSI":[10],"logic":[11,37],"family":[12],"in":[13,48,71],"standard":[14],"CMOS.":[15,73],"This":[16],"brief":[17],"proposes":[18],"an":[19,25],"unbalanced":[20],"pull-up/down":[21],"network,":[22],"together":[23],"with":[24,91,119],"inverse":[26],"narrow-width":[27],"technique,":[28],"to":[29,107],"improve":[30],"operating":[32],"speed":[33],"individual":[36],"cell.":[38],"Effective":[39],"logical":[40],"efforts":[41],"save":[42],"both":[43],"power":[44],"and":[45,54,80,99,109,112],"die":[46],"area":[47],"process":[50],"device":[52],"sizing":[53],"topology":[55],"optimization.":[56],"Three":[57],"experimental":[58],"14-tap":[59],"8-bit":[60],"finite":[61],"impulse":[62],"response":[63],"filters":[64],"optimized":[65,78],"for":[66],"ultralow-voltage":[67],"operation":[68],"were":[69],"fabricated":[70],"0.18-\u03bcm":[72],"Measurements":[74],"show":[75],"that":[76],"0.45":[79],"0.6":[81],"V":[82],"libraries":[83],"achieve":[84],"minimum":[85],"energy":[86],"operations":[87],"at":[88],"100":[89],"kHz,":[90],"figure-of-merit":[93],"0.365":[95],"(at":[96,101],"0.31":[97],"V)":[98],"0.4632":[100],"0.39":[102],"V),":[103],"respectively.":[104],"They":[105],"correspond":[106],"35.96%":[108],"18.74%":[110],"improvements,":[111],"overall":[114],"performances":[115],"are":[116],"well":[117],"comparable":[118],"state":[121],"art.":[124]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}