{"id":"https://openalex.org/W2170203810","doi":"https://doi.org/10.1109/tvlsi.2014.2387391","title":"Variability in Multistage Synchronizers","display_name":"Variability in Multistage Synchronizers","publication_year":2015,"publication_date":"2015-01-23","ids":{"openalex":"https://openalex.org/W2170203810","doi":"https://doi.org/10.1109/tvlsi.2014.2387391","mag":"2170203810"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2387391","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2387391","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091540517","display_name":"Salomon Beer","orcid":"https://orcid.org/0000-0001-6778-8216"},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"Salomon Beer","raw_affiliation_strings":["Department of Computer Engineering, Technion\u2014Israel Institute of Technology, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Technion\u2014Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037975154","display_name":"Jerome Cox","orcid":null},"institutions":[{"id":"https://openalex.org/I4210090993","display_name":"Blendics (United States)","ror":"https://ror.org/00drde038","country_code":"US","type":"company","lineage":["https://openalex.org/I4210090993"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jerome Cox","raw_affiliation_strings":["Blendics, St. Louis, MO, USA"],"affiliations":[{"raw_affiliation_string":"Blendics, St. Louis, MO, USA","institution_ids":["https://openalex.org/I4210090993"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010407295","display_name":"Ran Ginosar","orcid":null},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Ran Ginosar","raw_affiliation_strings":["Department of Electrical Engineering, Technion\u2014Israel Institute of Technology, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Technion\u2014Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067920810","display_name":"Tom Chaney","orcid":null},"institutions":[{"id":"https://openalex.org/I4210090993","display_name":"Blendics (United States)","ror":"https://ror.org/00drde038","country_code":"US","type":"company","lineage":["https://openalex.org/I4210090993"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tom Chaney","raw_affiliation_strings":["Blendics, St. Louis, MO, USA"],"affiliations":[{"raw_affiliation_string":"Blendics, St. Louis, MO, USA","institution_ids":["https://openalex.org/I4210090993"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053068007","display_name":"David M. Zar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210090993","display_name":"Blendics (United States)","ror":"https://ror.org/00drde038","country_code":"US","type":"company","lineage":["https://openalex.org/I4210090993"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David M. Zar","raw_affiliation_strings":["Blendics, St. Louis, MO, USA"],"affiliations":[{"raw_affiliation_string":"Blendics, St. Louis, MO, USA","institution_ids":["https://openalex.org/I4210090993"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5091540517"],"corresponding_institution_ids":["https://openalex.org/I174306211"],"apc_list":null,"apc_paid":null,"fwci":0.646,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.7011805,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"23","issue":"12","first_page":"2957","last_page":"2969"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.8819990158081055},{"id":"https://openalex.org/keywords/mean-time-between-failures","display_name":"Mean time between failures","score":0.7895991206169128},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7535679340362549},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6869933605194092},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5552769899368286},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5383736491203308},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.5081653594970703},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46393635869026184},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.45626285672187805},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4365169405937195},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4363335371017456},{"id":"https://openalex.org/keywords/upper-and-lower-bounds","display_name":"Upper and lower bounds","score":0.42899012565612793},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.41771912574768066},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3660847842693329},{"id":"https://openalex.org/keywords/failure-rate","display_name":"Failure rate","score":0.34775015711784363},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3352120816707611},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3034636378288269},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.24640104174613953},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.21595695614814758},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12614399194717407},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12433981895446777},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10517874360084534},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10262569785118103},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08506405353546143}],"concepts":[{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.8819990158081055},{"id":"https://openalex.org/C44154001","wikidata":"https://www.wikidata.org/wiki/Q754940","display_name":"Mean time between failures","level":3,"score":0.7895991206169128},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7535679340362549},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6869933605194092},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5552769899368286},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5383736491203308},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.5081653594970703},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46393635869026184},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.45626285672187805},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4365169405937195},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4363335371017456},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.42899012565612793},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.41771912574768066},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3660847842693329},{"id":"https://openalex.org/C163164238","wikidata":"https://www.wikidata.org/wiki/Q2737027","display_name":"Failure rate","level":2,"score":0.34775015711784363},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3352120816707611},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3034636378288269},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.24640104174613953},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.21595695614814758},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12614399194717407},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12433981895446777},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10517874360084534},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10262569785118103},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08506405353546143},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2387391","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2387391","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5799999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G5913329749","display_name":null,"funder_award_id":"0924010","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W149082927","https://openalex.org/W1545762351","https://openalex.org/W1913431666","https://openalex.org/W2007675081","https://openalex.org/W2007749646","https://openalex.org/W2012541825","https://openalex.org/W2043271913","https://openalex.org/W2083451059","https://openalex.org/W2099919186","https://openalex.org/W2106531538","https://openalex.org/W2110913706","https://openalex.org/W2117345564","https://openalex.org/W2118358623","https://openalex.org/W2136810784","https://openalex.org/W2139193411","https://openalex.org/W2155142658","https://openalex.org/W2155817938","https://openalex.org/W2158263501","https://openalex.org/W4211171470","https://openalex.org/W4253769920","https://openalex.org/W4254011844","https://openalex.org/W6632657505","https://openalex.org/W6671487899","https://openalex.org/W6683243724"],"related_works":["https://openalex.org/W2136810784","https://openalex.org/W1968296979","https://openalex.org/W2106531538","https://openalex.org/W1655066912","https://openalex.org/W2134530532","https://openalex.org/W4285814768","https://openalex.org/W2085344061","https://openalex.org/W3016151994","https://openalex.org/W4287816296","https://openalex.org/W2325117947"],"abstract_inverted_index":{"System-on-a-chip":[0],"designs":[1,60],"typically":[2],"employ":[3],"multiple":[4,29],"clock":[5,26,51,145],"domains":[6],"to":[7,18,45,78,89],"interface":[8],"several":[9],"externally":[10],"clocked":[11],"circuits":[12],"operating":[13],"at":[14],"different":[15,50],"frequencies":[16],"and":[17,21,84,104,140,148,189],"reduce":[19],"power":[20],"area":[22],"by":[23,160],"breaking":[24],"large":[25],"trees":[27],"into":[28],"small":[30],"ones.":[31],"The":[32,127],"principal":[33],"challenge":[34],"of":[35,82,87,129,144,162,173,176],"such":[36,92],"globally":[37],"asynchronous":[38],"locally":[39],"synchronous":[40],"architectures":[41],"is":[42,138,187,194],"the":[43,49,80,85,141,167,174],"need":[44],"reliably":[46],"communicate":[47],"between":[48,113],"domains.":[52],"To":[53],"achieve":[54],"high":[55],"reliability":[56],"margins":[57],"in":[58,62,91,101,183],"high-frequency":[59],"implemented":[61],"modern":[63],"process":[64,149,154],"technologies,":[65],"multistage":[66,136],"synchronizers":[67,137],"are":[68,151],"often":[69],"used.":[70],"In":[71],"this":[72],"paper,":[73],"we":[74],"develop":[75],"analytical":[76],"formulas":[77],"calculate":[79],"probability":[81,175],"failure":[83],"number":[86],"stages":[88],"use":[90,161],"synchronizers.":[93],"We":[94],"compare":[95],"our":[96],"model":[97,117],"with":[98,123],"those":[99],"reported":[100],"previous":[102],"publications":[103],"show":[105],"that":[106],"most":[107],"existing":[108],"models":[109],"underestimate":[110],"mean":[111],"time":[112,133],"failures":[114],"(MTBF).":[115],"Our":[116],"calculates":[118],"an":[119,130],"MTBF":[120],"lower":[121,192],"bound":[122,193],"significantly":[124],"smaller":[125],"margins.":[126],"concept":[128],"effective":[131],"resolution":[132],"constant":[134],"for":[135,166,180],"introduced":[139],"important":[142],"effects":[143,156],"duty":[146],"cycle":[147],"variability":[150,155],"addressed.":[152],"These":[153],"can":[157],"be":[158],"minimized":[159],"simple":[163,191],"design":[164],"rules":[165],"synchronizer.":[168],"For":[169],"safety-critical":[170],"applications,":[171],"calculation":[172],"a":[177,184,190],"failure-free":[178],"lifetime":[179],"all":[181],"products":[182],"production":[185],"run":[186],"developed":[188],"derived.":[195]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}