{"id":"https://openalex.org/W2112352821","doi":"https://doi.org/10.1109/tvlsi.2014.2385832","title":"Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization","display_name":"Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization","publication_year":2015,"publication_date":"2015-01-12","ids":{"openalex":"https://openalex.org/W2112352821","doi":"https://doi.org/10.1109/tvlsi.2014.2385832","mag":"2112352821"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2385832","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2385832","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047625300","display_name":"Jim Boley","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jim Boley","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA , USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA , USA#TAB#","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030134735","display_name":"Peter Beshay","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter Beshay","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA , USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA , USA#TAB#","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080557997","display_name":"Benton H. Calhoun","orcid":"https://orcid.org/0000-0002-3770-5050"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Benton Calhoun","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA , USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA , USA#TAB#","institution_ids":["https://openalex.org/I51556381"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I51556381"],"apc_list":null,"apc_paid":null,"fwci":0.5831,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.72076163,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"23","issue":"12","first_page":"3109","last_page":"3113"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7195268273353577},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6168898344039917},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5932344198226929},{"id":"https://openalex.org/keywords/boosting","display_name":"Boosting (machine learning)","score":0.5550565123558044},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5302027463912964},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.529816746711731},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4944455623626709},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.48238053917884827},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.48212528228759766},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4251987040042877},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4114101231098175},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3022816777229309},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26112478971481323},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24027079343795776},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2283014953136444},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12851041555404663},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12424728274345398}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7195268273353577},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6168898344039917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5932344198226929},{"id":"https://openalex.org/C46686674","wikidata":"https://www.wikidata.org/wiki/Q466303","display_name":"Boosting (machine learning)","level":2,"score":0.5550565123558044},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5302027463912964},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.529816746711731},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4944455623626709},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.48238053917884827},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.48212528228759766},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4251987040042877},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4114101231098175},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3022816777229309},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26112478971481323},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24027079343795776},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2283014953136444},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12851041555404663},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12424728274345398},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2385832","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2385832","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G8564455380","display_name":null,"funder_award_id":"2233.001","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1973081841","https://openalex.org/W2002612140","https://openalex.org/W2067168777","https://openalex.org/W2095913060","https://openalex.org/W2098320407","https://openalex.org/W2109579847","https://openalex.org/W2110664174","https://openalex.org/W2114330343","https://openalex.org/W2121621947","https://openalex.org/W2126918373","https://openalex.org/W2156520002","https://openalex.org/W2163676880","https://openalex.org/W2545471485","https://openalex.org/W3147064120","https://openalex.org/W3150016669","https://openalex.org/W3151909510","https://openalex.org/W4252004518","https://openalex.org/W6643245339"],"related_works":["https://openalex.org/W2119312496","https://openalex.org/W4247460323","https://openalex.org/W2537086382","https://openalex.org/W2107909712","https://openalex.org/W2153162275","https://openalex.org/W2079259690","https://openalex.org/W2108986771","https://openalex.org/W789543267","https://openalex.org/W2094295436","https://openalex.org/W2075972383"],"abstract_inverted_index":{"This":[0,23],"brief":[1,123],"presents":[2],"a":[3,18,49,73,80,90,98,145,160],"tool":[4,26,118],"for":[5,29,64],"optimizing":[6],"the":[7,25,30,58,66,87,105,156],"energy":[8,153],"and":[9,35,42,53,68,132],"delay":[10,169],"(E/D)":[11],"of":[12,32,51,79,89,158],"static":[13],"RAM":[14],"designs":[15],"to":[16,27,36,56,71,85,96,112,165],"meet":[17,72,97],"specific":[19,99],"die":[20,75,100],"yield":[21,39],"constraint.":[22],"allows":[24,124],"account":[28],"effects":[31],"process":[33,130],"variation":[34],"trade":[37],"off":[38],"with":[40],"performance":[41],"energy.":[43],"To":[44],"accomplish":[45],"this,":[46],"we":[47,109,141],"use":[48,78],"combination":[50],"simulation":[52],"modeling":[54],"techniques":[55],"determine":[57],"minimum":[59],"wordline":[60],"(WL)":[61],"pulsewidth":[62],"required":[63],"both":[65],"read":[67,168],"write":[69],"operations":[70],"user-specified":[74],"yield.":[76,101],"The":[77,117],"hierarchical":[81],"model":[82],"enables":[83],"us":[84],"calculate":[86],"E/D":[88],"full":[91],"macro":[92],"that":[93,143],"is":[94],"margined":[95],"By":[102],"sweeping":[103],"across":[104,126],"possible":[106],"design":[107],"space,":[108],"are":[110],"able":[111],"identify":[113],"Pareto":[114],"optimal":[115],"designs.":[116],"structure":[119],"described":[120],"in":[121,150],"this":[122,139],"comparison":[125],"different":[127],"array":[128],"topologies,":[129],"technologies,":[131],"circuit":[133],"choices":[134],"including":[135],"assist":[136],"methods.":[137],"Using":[138],"tool,":[140],"find":[142],"adding":[144],"WL":[146],"boosting":[147],"scheme":[148],"results":[149],"an":[151,166],"overall":[152],"savings,":[154],"despite":[155],"overhead":[157],"using":[159],"charge":[161],"pump":[162],"circuit,":[163],"due":[164],"improved":[167],"distribution.":[170]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
