{"id":"https://openalex.org/W2142267062","doi":"https://doi.org/10.1109/tvlsi.2014.2384740","title":"Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis","display_name":"Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis","publication_year":2015,"publication_date":"2015-03-24","ids":{"openalex":"https://openalex.org/W2142267062","doi":"https://doi.org/10.1109/tvlsi.2014.2384740","mag":"2142267062"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2384740","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2384740","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025663917","display_name":"Matteo Cuppini","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Matteo Cuppini","raw_affiliation_strings":["Advanced Research Center on Electronic Systems for Information and Communication Technologies, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Research Center on Electronic Systems for Information and Communication Technologies, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045668159","display_name":"Claudio Mucci","orcid":"https://orcid.org/0000-0002-4660-207X"},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Claudio Mucci","raw_affiliation_strings":["STMicroelectronics, Agrate Brianza, Italy","STMicroelectronics - Agrate Brianza, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate Brianza, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics - Agrate Brianza, Italy","institution_ids":["https://openalex.org/I131827901"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087194868","display_name":"Eleonora Franchi Scarselli","orcid":"https://orcid.org/0000-0001-6994-2088"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Eleonora Franchi Scarselli","raw_affiliation_strings":["Advanced Research Center on Electronic Systems for Information and Communication Technologies, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Research Center on Electronic Systems for Information and Communication Technologies, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3507,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.67349796,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"23","issue":"12","first_page":"3043","last_page":"3052"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6752333641052246},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6289020776748657},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5883587002754211},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5684822797775269},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.43685147166252136},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43304839730262756},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40830832719802856},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33771204948425293},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2177354097366333}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6752333641052246},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6289020776748657},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5883587002754211},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5684822797775269},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43685147166252136},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43304839730262756},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40830832719802856},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33771204948425293},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2177354097366333},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2014.2384740","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2384740","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:cris.unibo.it:11585/551007","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/551007","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1972887087","https://openalex.org/W1977545325","https://openalex.org/W1991856150","https://openalex.org/W2030922743","https://openalex.org/W2031937298","https://openalex.org/W2042639208","https://openalex.org/W2047143252","https://openalex.org/W2077476145","https://openalex.org/W2100209312","https://openalex.org/W2100580949","https://openalex.org/W2105306095","https://openalex.org/W2112357703","https://openalex.org/W2126255765","https://openalex.org/W2138383740","https://openalex.org/W2138840350","https://openalex.org/W2150022482","https://openalex.org/W2150098004","https://openalex.org/W2155316178","https://openalex.org/W2162628682","https://openalex.org/W2168493238","https://openalex.org/W3150544110","https://openalex.org/W4213060235","https://openalex.org/W6674802953"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2502691491","https://openalex.org/W3142211975","https://openalex.org/W1879443270","https://openalex.org/W2018912978","https://openalex.org/W2130914040","https://openalex.org/W2119122672","https://openalex.org/W4292904049"],"abstract_inverted_index":{"Embedded":[0],"field":[1],"programmable":[2,131],"gate":[3],"arrays":[4],"(eFPGA)":[5],"can":[6],"provide":[7],"modern":[8],"systems-on-a-chip":[9],"(SoCs)":[10],"with":[11,37],"the":[12,17,26,67,70,79,83,130,183,198],"flexibility":[13,39],"required":[14],"to":[15,65,91,128,187,196],"face":[16],"growth":[18],"of":[19,42,69,77,115,143,177,182],"nonrecurring":[20],"engineering":[21],"and":[22,45,109,138,162],"manufacturing":[23],"costs.":[24],"On":[25],"other":[27],"hand,":[28],"SoC":[29],"designers":[30,64,186],"usually":[31],"perceive":[32],"eFPGAs":[33,90],"as":[34,53,193,195],"area-hungry":[35],"IPs":[36],"poor":[38],"in":[40],"terms":[41],"performance,":[43],"power":[44],"area":[46,72,204],"tradeoff":[47],"since":[48,133],"they":[49],"are":[50],"typically":[51],"available":[52,151],"custom-designed":[54],"hard":[55],"macros.":[56],"In":[57,96],"this":[58,97,134],"scenario,":[59],"technology":[60,80],"scaling":[61],"is":[62,118],"allowing":[63],"reduce":[66],"impact":[68],"eFPGA":[71,105,145,173],"gap,":[73],"while":[74],"effective":[75],"exploitation":[76],"all":[78],"options":[81],"(e.g.,":[82],"transistor":[84],"threshold)":[85],"entails":[86],"moving":[87],"toward":[88],"soft-core":[89,104],"match":[92],"specific":[93],"application":[94],"needs.":[95],"paper,":[98],"we":[99,120],"propose":[100],"an":[101],"look-up":[102],"table-based":[103],"featuring":[106],"a":[107,123,136,147,171,202],"synthesizable":[108,137],"parametric":[110],"architecture.":[111,140],"A":[112],"key":[113],"point":[114],"our":[116,144],"proposal":[117],"that":[119],"have":[121],"adopted":[122],"multistage":[124],"switching":[125],"network":[126],"(MSSN)":[127],"implement":[129],"interconnect,":[132],"ensures":[135],"congestion-free":[139],"Quantitative":[141],"evaluation":[142,167],"shows":[146],"significantly":[148],"wide":[149],"design-space":[150],"on":[152],"very":[153],"different":[154,180],"technologies":[155],"(we":[156],"experimented":[157],"STMicroelectronics":[158],"CMOS":[159],"65":[160],"nm":[161],"BCD9s":[163],"0.11":[164],"\u03bcm).":[165],"Application-driven":[166],"showed":[168],"how":[169],"for":[170,201],"fixed":[172],"size":[174],"(i.e.,":[175],"number":[176],"logic":[178],"blocks)":[179],"configurations":[181],"MSSN":[184],"allow":[185],"speed":[188],"up":[189],"performance":[190],"by":[191],"20/60%,":[192],"well":[194],"maximize":[197],"computational":[199],"density":[200],"given":[203],"budget.":[205]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}