{"id":"https://openalex.org/W2123159753","doi":"https://doi.org/10.1109/tvlsi.2014.2384042","title":"Modeling and Layout Optimization for Tapered TSVs","display_name":"Modeling and Layout Optimization for Tapered TSVs","publication_year":2015,"publication_date":"2015-01-14","ids":{"openalex":"https://openalex.org/W2123159753","doi":"https://doi.org/10.1109/tvlsi.2014.2384042","mag":"2123159753"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2384042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2384042","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064115741","display_name":"Tiantao Lu","orcid":"https://orcid.org/0000-0003-4431-811X"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tiantao Lu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, USA","Dept. of Electrical & Comput. Eng., Univ. of Maryland, College Park, MD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, USA","institution_ids":["https://openalex.org/I66946132"]},{"raw_affiliation_string":"Dept. of Electrical & Comput. Eng., Univ. of Maryland, College Park, MD, USA","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089770783","display_name":"Ankur Srivastava","orcid":"https://orcid.org/0000-0002-5445-904X"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ankur Srivastava","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, USA","Dept. of Electrical & Comput. Eng., Univ. of Maryland, College Park, MD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, USA","institution_ids":["https://openalex.org/I66946132"]},{"raw_affiliation_string":"Dept. of Electrical & Comput. Eng., Univ. of Maryland, College Park, MD, USA","institution_ids":["https://openalex.org/I66946132"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I66946132"],"apc_list":null,"apc_paid":null,"fwci":1.7492,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.86375307,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"23","issue":"12","first_page":"3129","last_page":"3132"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49046608805656433},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.43848085403442383},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.41200006008148193},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33326607942581177},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24429503083229065},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23105257749557495}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49046608805656433},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43848085403442383},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.41200006008148193},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33326607942581177},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24429503083229065},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23105257749557495}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2384042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2384042","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3588651776","display_name":"CIF: SMALL: Information Theoretic Multi-Core Processor Thermal Profile Estimation","funder_award_id":"0917057","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1978112218","https://openalex.org/W2006490754","https://openalex.org/W2079367006","https://openalex.org/W2102256773","https://openalex.org/W2110504571","https://openalex.org/W2113453347","https://openalex.org/W2133365606","https://openalex.org/W2163322466","https://openalex.org/W2166150228","https://openalex.org/W2170070894","https://openalex.org/W3146892808","https://openalex.org/W4244052412"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W4283025278","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W2050492524","https://openalex.org/W2376932109","https://openalex.org/W2998315020","https://openalex.org/W2104790384"],"abstract_inverted_index":{"Through-silicon-via":[0],"(TSV)":[1],"offers":[2],"vertical":[3],"connections":[4],"for":[5,31,85,107],"3-D":[6],"ICs.":[7],"Due":[8],"to":[9,20,24,114,134,159],"its":[10,53],"large":[11],"dimensions":[12],"and":[13,29,52,92,129,171,177],"nonideal":[14],"etching":[15],"process,":[16],"TSVs":[17,38,57,73,123],"layout":[18],"needs":[19],"be":[21],"carefully":[22],"optimized":[23],"balance":[25],"peak":[26,126,146,168],"current":[27,64,82,97,127,147,169],"density":[28,83,98,128,148,170],"delay":[30,138,141],"digital":[32],"circuit.":[33],"This":[34],"brief":[35],"investigates":[36],"the":[37,56,63,96,103,145,161,175],"tapering":[39,124],"effect":[40,66],"(which":[41],"is":[42,67,157],"an":[43],"inevitable":[44],"byproduct":[45],"of":[46,122],"deep":[47],"reactive":[48],"Ion":[49],"etching-based":[50],"manufacturing)":[51],"impact":[54,121],"on":[55,125],"electrical":[58],"properties.":[59],"We":[60,78,110],"show":[61],"that":[62],"crowding":[65],"more":[68],"severe":[69],"in":[70,94],"realistic":[71],"tapered":[72,86],"than":[74],"ideal":[75],"cylindrical":[76,108],"TSVs.":[77,109],"propose":[79],"a":[80,116],"nonuniform":[81],"model":[84,113,142],"TSVs,":[87],"which":[88,165],"achieves":[89],"considerable":[90],"accuracy":[91],"speedup":[93],"estimating":[95],"distribution,":[99],"when":[100],"compared":[101],"with":[102],"existing":[104],"models":[105],"developed":[106],"apply":[111],"our":[112],"perform":[115],"detailed":[117],"study":[118],"on:":[119],"1)":[120],"2)":[130],"wire":[131,163],"sizing":[132],"problem":[133],"minimize":[135],"TSV-involved":[136],"path":[137],"under":[139],"second-order":[140],"while":[143],"keeping":[144],"within":[149],"tolerable":[150],"levels.":[151],"A":[152],"new":[153],"dynamic":[154],"programming-based":[155],"heuristic":[156],"proposed":[158],"find":[160],"optimal":[162],"configuration,":[164],"reduces":[166],"both":[167],"delay,":[172],"thereby":[173],"improving":[174],"reliability":[176],"performance.":[178]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}