{"id":"https://openalex.org/W2085737637","doi":"https://doi.org/10.1109/tvlsi.2014.2377013","title":"Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework","display_name":"Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework","publication_year":2015,"publication_date":"2015-01-06","ids":{"openalex":"https://openalex.org/W2085737637","doi":"https://doi.org/10.1109/tvlsi.2014.2377013","mag":"2085737637"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2377013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2377013","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017101827","display_name":"Liuxi Qian","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Liuxi Qian","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039204202","display_name":"Zhaori Bi","orcid":"https://orcid.org/0000-0002-7315-3150"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhaori Bi","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054960059","display_name":"Dian Zhou","orcid":"https://orcid.org/0000-0002-2648-5232"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN","US"],"is_corresponding":false,"raw_author_name":"Dian Zhou","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA","Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064213921","display_name":"Xuan Zeng","orcid":"https://orcid.org/0000-0002-8097-4053"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuan Zeng","raw_affiliation_strings":["ASIC and System State Key Laboratory, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"ASIC and System State Key Laboratory, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5017101827"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.9864,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.79240731,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"23","issue":"11","first_page":"2595","last_page":"2605"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.7158583402633667},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.602933406829834},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5921899080276489},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4959312379360199},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.48268961906433105},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.43400606513023376},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4216157793998718},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24872678518295288},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24798136949539185},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08921226859092712}],"concepts":[{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.7158583402633667},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.602933406829834},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5921899080276489},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4959312379360199},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.48268961906433105},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.43400606513023376},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4216157793998718},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24872678518295288},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24798136949539185},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08921226859092712},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2377013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2377013","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Reduced inequalities","score":0.7400000095367432,"id":"https://metadata.un.org/sdg/10"}],"awards":[{"id":"https://openalex.org/G1894967140","display_name":null,"funder_award_id":"637163","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"},{"id":"https://openalex.org/G2394728413","display_name":null,"funder_award_id":"13XD1401100","funder_id":"https://openalex.org/F4320321885","funder_display_name":"Science and Technology Commission of Shanghai Municipality"},{"id":"https://openalex.org/G2955192245","display_name":null,"funder_award_id":"1115556","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G3819284956","display_name":null,"funder_award_id":"525870","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"},{"id":"https://openalex.org/G6145200470","display_name":null,"funder_award_id":"2011CB309701","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320321885","display_name":"Science and Technology Commission of Shanghai Municipality","ror":"https://ror.org/03kt66j61"},{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":50,"referenced_works":["https://openalex.org/W60873545","https://openalex.org/W147475332","https://openalex.org/W1516032497","https://openalex.org/W1595159159","https://openalex.org/W1637203448","https://openalex.org/W1639032689","https://openalex.org/W1669104078","https://openalex.org/W1872183006","https://openalex.org/W1957272849","https://openalex.org/W1998674867","https://openalex.org/W2000359198","https://openalex.org/W2012300240","https://openalex.org/W2014337138","https://openalex.org/W2015848108","https://openalex.org/W2030422718","https://openalex.org/W2031858669","https://openalex.org/W2033168046","https://openalex.org/W2041333819","https://openalex.org/W2044672662","https://openalex.org/W2055936709","https://openalex.org/W2093625674","https://openalex.org/W2100128641","https://openalex.org/W2100905115","https://openalex.org/W2102933388","https://openalex.org/W2108732866","https://openalex.org/W2114014957","https://openalex.org/W2114750951","https://openalex.org/W2127886717","https://openalex.org/W2138744296","https://openalex.org/W2144133630","https://openalex.org/W2145633829","https://openalex.org/W2146080060","https://openalex.org/W2153267648","https://openalex.org/W2153643257","https://openalex.org/W2154507680","https://openalex.org/W2155761685","https://openalex.org/W2157522838","https://openalex.org/W2169047810","https://openalex.org/W2172440946","https://openalex.org/W2210784489","https://openalex.org/W2289329755","https://openalex.org/W2293734310","https://openalex.org/W2490904451","https://openalex.org/W2751298281","https://openalex.org/W3023540311","https://openalex.org/W3137715965","https://openalex.org/W4252924468","https://openalex.org/W6636964851","https://openalex.org/W6654629932","https://openalex.org/W7018010582"],"related_works":["https://openalex.org/W3154683910","https://openalex.org/W1846734616","https://openalex.org/W3134543635","https://openalex.org/W2359532622","https://openalex.org/W2921318524","https://openalex.org/W2377571686","https://openalex.org/W4380988671","https://openalex.org/W1925657225","https://openalex.org/W2000469917","https://openalex.org/W4226309346"],"abstract_inverted_index":{"Optimization-simulation":[0],"loop-based":[1],"method":[2],"is":[3,13,89,108,160],"popular":[4],"and":[5,52,65,134,140,146],"efficient":[6],"in":[7,19,69,91,115,179],"design":[8,40],"migration/reuse":[9],"automation.":[10],"However,":[11],"it":[12],"only":[14,86],"restricted":[15],"to":[16,22,45,62,76,110,148,162],"be":[17],"used":[18,147,161],"block-level":[20],"due":[21],"the":[23,49,73,78,112,150,164,172],"complexity":[24],"of":[25,59],"current":[26],"mixed-signal":[27,38,155],"system.":[28],"This":[29,118],"paper":[30],"presents":[31],"a":[32,121,132],"hierarchical":[33],"methodology":[34,174],"for":[35,125,130],"efficiently":[36,175],"migrating":[37],"circuit":[39,51],"from":[41],"one":[42,87],"technology":[43,181],"node":[44],"another,":[46],"while":[47,95],"keeping":[48],"same":[50],"layout":[53],"topologies.":[54],"It":[55],"utilizes":[56],"two":[57],"stages":[58],"optimization":[60,106],"processes":[61],"automatically":[63],"resize":[64,111],"refine":[66],"device":[67],"dimensions":[68],"target":[70,180],"technology.":[71],"In":[72],"first":[74],"stage,":[75],"avoid":[77],"costly":[79],"simulation":[80,185],"time":[81],"without":[82],"scarifying":[83],"systematical":[84],"functionality,":[85],"block":[88,114],"represented":[90],"transistor":[92],"level":[93],"(TL),":[94],"other":[96],"blocks":[97],"are":[98,144],"replaced":[99],"with":[100,182,189],"behavioral":[101],"models.":[102],"The":[103,167],"multistart":[104],"global":[105],"technique":[107],"applied":[109],"TL":[113],"systematic":[116],"connection.":[117],"stage":[119],"provides":[120],"good":[122],"initial":[123],"point":[124],"next":[126],"system-level":[127],"refinement.":[128],"Moreover,":[129],"obtaining":[131],"process":[133,141],"parasitic":[135,139],"closure":[136],"solution,":[137],"both":[138],"variation":[142],"effects":[143],"explored":[145],"constrain":[149],"schematic":[151],"migration.":[152],"A":[153],"representative":[154],"system,":[156],"charge-pump":[157],"phase-locked":[158],"loop,":[159],"validate":[163],"proposed":[165,173],"methodology.":[166],"experimental":[168],"results":[169],"show":[170],"that":[171],"generates":[176],"quality":[177],"designs":[178],"much":[183],"less":[184],"iterations,":[186],"when":[187],"comparing":[188],"recent":[190],"available":[191],"approaches.":[192]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}