{"id":"https://openalex.org/W2063295745","doi":"https://doi.org/10.1109/tvlsi.2014.2362150","title":"Trainable and Low-Cost SMO Pattern Classifier Implemented via MCMC and SFBS Technologies","display_name":"Trainable and Low-Cost SMO Pattern Classifier Implemented via MCMC and SFBS Technologies","publication_year":2014,"publication_date":"2014-11-11","ids":{"openalex":"https://openalex.org/W2063295745","doi":"https://doi.org/10.1109/tvlsi.2014.2362150","mag":"2063295745"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2362150","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2362150","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018575006","display_name":"Chih\u2010Hsiang Peng","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chih-Hsiang Peng","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017800511","display_name":"Ta-Wen Kuan","orcid":"https://orcid.org/0000-0002-0789-3716"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ta-Wen Kuan","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111831974","display_name":"Po\u2010Chuan Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I1049131","display_name":"Tung Fang Design Institute","ror":"https://ror.org/05v5xnv04","country_code":"TW","type":"education","lineage":["https://openalex.org/I1049131"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Chuan Lin","raw_affiliation_strings":["Multimedia and Digital System Design Laboratory, Tung-Fang Design Institute, Kaohsiung, Taiwan","Department of Digital Game and Animation DesignMultimedia and Digital System Design Laboratory, Tung-Fang Design Institute, Kaohsiung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Multimedia and Digital System Design Laboratory, Tung-Fang Design Institute, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I1049131"]},{"raw_affiliation_string":"Department of Digital Game and Animation DesignMultimedia and Digital System Design Laboratory, Tung-Fang Design Institute, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I1049131"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088136847","display_name":"Jhing-Fa Wang","orcid":"https://orcid.org/0009-0000-2816-2480"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jhing-Fa Wang","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041715121","display_name":"Guo-Ji Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Guo-Ji Wu","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)","institution_ids":["https://openalex.org/I91807558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6302,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.70428778,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"23","issue":"10","first_page":"2295","last_page":"2306"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9919999837875366,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.593154788017273},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5375300049781799},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5071353912353516},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3840685188770294},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3756827712059021},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.34945034980773926},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2051190435886383}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.593154788017273},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5375300049781799},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5071353912353516},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3840685188770294},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3756827712059021},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.34945034980773926},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2051190435886383},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2362150","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2362150","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1535034008","https://openalex.org/W1574862351","https://openalex.org/W1981784429","https://openalex.org/W2030933600","https://openalex.org/W2031601132","https://openalex.org/W2035371449","https://openalex.org/W2054178868","https://openalex.org/W2054496661","https://openalex.org/W2059866937","https://openalex.org/W2068384573","https://openalex.org/W2073546306","https://openalex.org/W2090324313","https://openalex.org/W2094144369","https://openalex.org/W2096776357","https://openalex.org/W2098133383","https://openalex.org/W2098544339","https://openalex.org/W2103539323","https://openalex.org/W2107611395","https://openalex.org/W2109238007","https://openalex.org/W2113844397","https://openalex.org/W2116173306","https://openalex.org/W2119821739","https://openalex.org/W2120695048","https://openalex.org/W2123100368","https://openalex.org/W2130719360","https://openalex.org/W2134010649","https://openalex.org/W2139634554","https://openalex.org/W2157965742","https://openalex.org/W2162626712","https://openalex.org/W2163584947","https://openalex.org/W2166613240","https://openalex.org/W4239510810","https://openalex.org/W6632075938","https://openalex.org/W6676763481","https://openalex.org/W6677140251"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,10,109],"multicore":[4],"and":[5,9,12,37,45,72,84,93,112,119,135],"multichannel":[6,57],"(MCMC)":[7],"technology":[8,29],"synchronous":[11,71],"forward-backward":[13,73],"scheduling":[14],"(SFBS)":[15],"for":[16,75,88],"the":[17,68,97,100,105,127,132],"cost":[18,128],"reduction":[19],"of":[20],"sequential":[21],"minimal":[22],"optimization":[23],"trainable":[24],"pattern":[25],"classifier.":[26],"The":[27,123],"MCMC":[28,83],"uses":[30,70],"multiple":[31],"processing":[32],"cores":[33],"that":[34,104],"are":[35,86],"self-reconfigurable":[36],"preconfigurable.":[38],"For":[39,78],"different":[40,61],"functions,":[41],"five":[42],"self-configurable":[43],"modes":[44,48],"four":[46],"preconfigurable":[47],"can":[49],"be":[50],"combined":[51,87],"to":[52],"achieve":[53],"high":[54],"flexibility.":[55],"A":[56],"hierarchical":[58],"architecture":[59,107,134],"enables":[60],"transfer":[62],"rates.":[63],"To":[64],"minimize":[65],"communication":[66],"cost,":[67],"SFBS":[69,85],"counting":[74],"data":[76],"scheduling.":[77],"implementation":[79],"in":[80,90],"reconfigurable":[81],"FPGAs,":[82],"use":[89],"synthesis,":[91],"placement,":[92],"routing.":[94],"Compared":[95],"with":[96],"baseline":[98],"design,":[99],"emulation":[101],"results":[102,125],"show":[103],"proposed":[106,133],"has":[108],"low":[110,113],"area":[111],"power":[114],"costs":[115],"(5755":[116],"logic":[117],"elements":[118],"195":[120],"mW),":[121],"respectively.":[122],"experimental":[124],"confirm":[126],"improvement":[129],"achieved":[130],"by":[131],"methods.":[136]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
