{"id":"https://openalex.org/W2080635351","doi":"https://doi.org/10.1109/tvlsi.2014.2360801","title":"Two-Port PCM Architecture for Network Processing","display_name":"Two-Port PCM Architecture for Network Processing","publication_year":2014,"publication_date":"2014-12-23","ids":{"openalex":"https://openalex.org/W2080635351","doi":"https://doi.org/10.1109/tvlsi.2014.2360801","mag":"2080635351"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2360801","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2360801","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100775744","display_name":"Jiayin Li","orcid":"https://orcid.org/0000-0003-4798-082X"},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiayin Li","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008992388","display_name":"David B. Dgien","orcid":null},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David B. Dgien","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062996400","display_name":"Nathan Altay Hunter","orcid":null},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nathan Altay Hunter","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057418391","display_name":"Yirong Zhao","orcid":null},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yirong Zhao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021693439","display_name":"Kartik Mohanram","orcid":null},"institutions":[{"id":"https://openalex.org/I170201317","display_name":"University of Pittsburgh","ror":"https://ror.org/01an3r305","country_code":"US","type":"education","lineage":["https://openalex.org/I170201317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kartik Mohanram","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I170201317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I170201317"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.16068502,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"23","issue":"10","first_page":"2135","last_page":"2148"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8204563856124878},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5703878998756409},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5279354453086853},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.517259418964386},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5080931186676025},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.49961113929748535},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4560004770755768},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.44086509943008423},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.41655629873275757},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40263867378234863},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36974281072616577},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.335938423871994},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27036792039871216},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.2679001986980438},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.20807409286499023}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8204563856124878},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5703878998756409},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5279354453086853},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.517259418964386},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5080931186676025},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.49961113929748535},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4560004770755768},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.44086509943008423},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.41655629873275757},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40263867378234863},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36974281072616577},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.335938423871994},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27036792039871216},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2679001986980438},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.20807409286499023}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2360801","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2360801","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G262062211","display_name":null,"funder_award_id":"CCF-1208933","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":52,"referenced_works":["https://openalex.org/W1500589160","https://openalex.org/W1532601392","https://openalex.org/W1923047508","https://openalex.org/W1976515507","https://openalex.org/W1979866689","https://openalex.org/W1983826793","https://openalex.org/W1984381469","https://openalex.org/W1986418066","https://openalex.org/W1987335040","https://openalex.org/W2000270805","https://openalex.org/W2010202670","https://openalex.org/W2010795939","https://openalex.org/W2015477844","https://openalex.org/W2026517532","https://openalex.org/W2029384854","https://openalex.org/W2032091965","https://openalex.org/W2035934766","https://openalex.org/W2041588416","https://openalex.org/W2050860123","https://openalex.org/W2063757125","https://openalex.org/W2076239964","https://openalex.org/W2082070657","https://openalex.org/W2085273892","https://openalex.org/W2097823832","https://openalex.org/W2100600184","https://openalex.org/W2101349595","https://openalex.org/W2101810455","https://openalex.org/W2112753327","https://openalex.org/W2113901513","https://openalex.org/W2121795083","https://openalex.org/W2124064997","https://openalex.org/W2126370767","https://openalex.org/W2127414654","https://openalex.org/W2130279523","https://openalex.org/W2132792130","https://openalex.org/W2137108044","https://openalex.org/W2140144029","https://openalex.org/W2142571770","https://openalex.org/W2147539449","https://openalex.org/W2147639869","https://openalex.org/W2154695439","https://openalex.org/W2161091390","https://openalex.org/W2163083688","https://openalex.org/W2165697076","https://openalex.org/W2613173048","https://openalex.org/W3152304157","https://openalex.org/W4234103901","https://openalex.org/W4246347327","https://openalex.org/W6644353497","https://openalex.org/W6650716031","https://openalex.org/W6659459035","https://openalex.org/W6671183045"],"related_works":["https://openalex.org/W4285245242","https://openalex.org/W1993089791","https://openalex.org/W3029446734","https://openalex.org/W2155373950","https://openalex.org/W2587873888","https://openalex.org/W2057195881","https://openalex.org/W2534610203","https://openalex.org/W2782503170","https://openalex.org/W3093911585","https://openalex.org/W2044064773"],"abstract_inverted_index":{"Asymmetry":[0],"in":[1,44,121],"read/write":[2],"access":[3,47,51,129,178],"latencies,":[4],"which":[5,40],"leads":[6],"to":[7,64,74,111,142,175,226],"issues":[8],"of":[9,23,107,123,171,193],"blocking":[10,112],"writes":[11],"and":[12,36,131,147,186,199,209],"low":[13],"throughput":[14,58],"performance,":[15,59],"is":[16,160],"a":[17,80,87,137],"common":[18],"challenge":[19],"impeding":[20],"the":[21,71,105,117,144,156,163,168,176,191,212,217],"integration":[22],"emerging":[24],"nonvolatile":[25],"memory":[26,48,52,54,72,83,91,164],"technologies":[27],"into":[28],"high-performance":[29,95,152],"computing":[30],"systems.":[31],"Approaches":[32],"based":[33],"on":[34,86],"multiporting":[35],"virtually":[37,81,157],"pipelined":[38,82,158],"architectures,":[39],"have":[41],"been":[42],"studied":[43],"static":[45],"random":[46,50],"(SRAM)/dynamic":[49],"(DRAM)/hybrid-SRAM/DRAM":[53],"systems":[55],"for":[56,94,128,151,184,232],"high":[57],"provide":[60,143],"an":[61],"attractive":[62],"means":[63],"overcome":[65],"these":[66],"challenges":[67],"through":[68,180],"innovations":[69,214],"spanning":[70],"cell":[73,102,119],"architecture":[75,84,159,195],"levels.":[76],"This":[77],"paper":[78],"describes":[79],"built":[85],"two-port":[88,100,118,138],"phase":[89],"change":[90],"(PCM)":[92],"substrate":[93],"networking":[96,153],"applications.":[97,154],"The":[98],"proposed":[99,213],"PCM":[101,139,231],"significantly":[103],"reduces":[104],"probability":[106],"bank":[108,140,148],"conflicts":[109],"due":[110,174],"writes.":[113],"We":[114,134,189],"comprehensively":[115],"evaluate":[116],"design":[120,141],"terms":[122],"programming":[124],"current,":[125],"voltage":[126],"pumping":[127],"transistors,":[130],"area":[132],"overhead.":[133],"also":[135],"propose":[136],"large":[145],"bandwidth":[146],"parallelism":[149],"critical":[150],"Furthermore,":[155],"implemented":[161],"at":[162],"controller":[165],"level,":[166],"eliminating":[167],"extra":[169],"delay":[170,221],"read":[172,185,219],"requests":[173],"asymmetrical":[177],"latency":[179],"separate":[181],"reservation":[182],"tables":[183],"write":[187],"requests.":[188],"analyze":[190],"performance":[192],"this":[194],"using":[196,207],"queuing":[197],"theory":[198],"statistical":[200],"information":[201],"obtained":[202],"by":[203,222],"processing":[204],"packet":[205],"traces":[206],"PacketBench,":[208],"show":[210],"that":[211],"can":[215],"reduce":[216],"expected":[218],"(write)":[220],"12-$40\\times":[223],"$":[224],"(up":[225],"14%)":[227],"over":[228],"conventional":[229],"single-port":[230],"110%-170%":[233],"additional":[234],"area.":[235]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}