{"id":"https://openalex.org/W2079836022","doi":"https://doi.org/10.1109/tvlsi.2014.2346712","title":"Efficient Hardware Implementation of Encoder and Decoder for Golay Code","display_name":"Efficient Hardware Implementation of Encoder and Decoder for Golay Code","publication_year":2014,"publication_date":"2014-08-22","ids":{"openalex":"https://openalex.org/W2079836022","doi":"https://doi.org/10.1109/tvlsi.2014.2346712","mag":"2079836022"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2346712","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2346712","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075977257","display_name":"Satyabrata Sarangi","orcid":"https://orcid.org/0000-0003-2988-3698"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Satyabrata Sarangi","raw_affiliation_strings":["Department of Electronics and Electrical Communication Engineering, IIT Kharagpur, Kharagpur, India","[Department of Electronics and Electrical communication Engineering, IIT Kharagpur, Kharagpur, India]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Communication Engineering, IIT Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"[Department of Electronics and Electrical communication Engineering, IIT Kharagpur, Kharagpur, India]","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102708076","display_name":"Swapna Banerjee","orcid":"https://orcid.org/0000-0001-9971-2013"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Swapna Banerjee","raw_affiliation_strings":["Department of Electronics and Electrical Communication Engineering, IIT Kharagpur, Kharagpur, India","[Department of Electronics and Electrical communication Engineering, IIT Kharagpur, Kharagpur, India]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Communication Engineering, IIT Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"[Department of Electronics and Electrical communication Engineering, IIT Kharagpur, Kharagpur, India]","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5075977257"],"corresponding_institution_ids":["https://openalex.org/I145894827"],"apc_list":null,"apc_paid":null,"fwci":3.1033,"has_fulltext":false,"cited_by_count":32,"citation_normalized_percentile":{"value":0.9246848,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"23","issue":"9","first_page":"1965","last_page":"1968"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10964","display_name":"Wireless Communication Security Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/binary-golay-code","display_name":"Binary Golay code","score":0.9447212219238281},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.7772029042243958},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.7146929502487183},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6833218336105347},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6714329123497009},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.5407346487045288},{"id":"https://openalex.org/keywords/ternary-golay-code","display_name":"Ternary Golay code","score":0.5199531316757202},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.48972633481025696},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4537213444709778},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.41677093505859375},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3984338939189911},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3284221887588501},{"id":"https://openalex.org/keywords/code-rate","display_name":"Code rate","score":0.2655176520347595},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.19249680638313293},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18121424317359924},{"id":"https://openalex.org/keywords/systematic-code","display_name":"Systematic code","score":0.1384921669960022},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.0653715431690216}],"concepts":[{"id":"https://openalex.org/C165293857","wikidata":"https://www.wikidata.org/wiki/Q1534522","display_name":"Binary Golay code","level":2,"score":0.9447212219238281},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.7772029042243958},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.7146929502487183},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6833218336105347},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6714329123497009},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.5407346487045288},{"id":"https://openalex.org/C108906091","wikidata":"https://www.wikidata.org/wiki/Q7702927","display_name":"Ternary Golay code","level":5,"score":0.5199531316757202},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.48972633481025696},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4537213444709778},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.41677093505859375},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3984338939189911},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3284221887588501},{"id":"https://openalex.org/C206468330","wikidata":"https://www.wikidata.org/wiki/Q834373","display_name":"Code rate","level":3,"score":0.2655176520347595},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.19249680638313293},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18121424317359924},{"id":"https://openalex.org/C70992990","wikidata":"https://www.wikidata.org/wiki/Q1681587","display_name":"Systematic code","level":4,"score":0.1384921669960022},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0653715431690216},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2346712","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2346712","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1517974013","https://openalex.org/W1820288152","https://openalex.org/W1972484744","https://openalex.org/W1983853338","https://openalex.org/W1986602475","https://openalex.org/W1990933154","https://openalex.org/W1997709017","https://openalex.org/W2029900030","https://openalex.org/W2083351442","https://openalex.org/W2090511433","https://openalex.org/W2092182511","https://openalex.org/W2098066524","https://openalex.org/W2102886290","https://openalex.org/W2117954347","https://openalex.org/W2119225661","https://openalex.org/W2134030092","https://openalex.org/W2147202711","https://openalex.org/W2149286506","https://openalex.org/W2166380727","https://openalex.org/W2178768557","https://openalex.org/W2224888445","https://openalex.org/W2538174359","https://openalex.org/W2542961187","https://openalex.org/W2969271653","https://openalex.org/W3119473442","https://openalex.org/W6679746657","https://openalex.org/W6684722547","https://openalex.org/W6788737937"],"related_works":["https://openalex.org/W2178768557","https://openalex.org/W2092182511","https://openalex.org/W1996248169","https://openalex.org/W2119225661","https://openalex.org/W2564530319","https://openalex.org/W1963497077","https://openalex.org/W2349436890","https://openalex.org/W2392571380","https://openalex.org/W2132559602","https://openalex.org/W2079836022"],"abstract_inverted_index":{"This":[0,68],"brief":[1,69],"lays":[2],"out":[3],"cyclic":[4],"redundancy":[5],"check-based":[6],"encoding":[7,16],"scheme":[8],"and":[9,36,54,74,102],"presents":[10,71],"an":[11,72,88,130],"efficient":[12],"implementation":[13],"of":[14,108,134],"the":[15,27,109,124],"algorithm":[17],"in":[18,56,113,150],"field":[19],"programmable":[20],"gate":[21],"array":[22],"(FPGA)":[23],"prototype":[24],"for":[25,59,78,97,127,146],"both":[26],"binary":[28,38,80],"Golay":[29,39,60,81],"code":[30,40,82],"(G":[31,41],"<sub":[32,42],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[33,43],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">23</sub>":[34],")":[35],"extended":[37,79],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">24</sub>":[44],").":[45],"High":[46],"speed":[47],"with":[48],"low-latency":[49],"architecture":[50,77,96,126],"has":[51,103,129],"been":[52],"designed":[53],"implemented":[55],"Virtex-4":[57],"FPGA":[58],"encoder":[61,117],"without":[62],"incorporating":[63],"linear":[64],"feedback":[65],"shift":[66],"register.":[67],"also":[70],"optimized":[73],"low-complexity":[75],"decoding":[76,92],"(24,":[83],"12,":[84],"8)":[85],"based":[86],"on":[87],"incomplete":[89],"maximum":[90],"likelihood":[91],"scheme.":[93],"The":[94,116,137],"proposed":[95,125,138],"decoder":[98,128],"occupies":[99],"less":[100],"area":[101],"lower":[104],"latency":[105],"than":[106],"some":[107],"recent":[110],"work":[111],"published":[112],"this":[114],"area.":[115],"module":[118],"runs":[119],"at":[120],"238.575":[121],"MHz,":[122],"while":[123],"operating":[131],"clock":[132],"frequency":[133],"195.028":[135],"MHz.":[136],"hardware":[139],"modules":[140],"may":[141],"be":[142],"a":[143,155],"good":[144],"candidate":[145],"forward":[147],"error":[148],"correction":[149],"communication":[151],"link,":[152],"which":[153],"demands":[154],"high-speed":[156],"system.":[157]},"counts_by_year":[{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}