{"id":"https://openalex.org/W1995607470","doi":"https://doi.org/10.1109/tvlsi.2014.2341610","title":"A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors","display_name":"A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors","publication_year":2014,"publication_date":"2014-08-11","ids":{"openalex":"https://openalex.org/W1995607470","doi":"https://doi.org/10.1109/tvlsi.2014.2341610","mag":"1995607470"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2341610","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2341610","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005550142","display_name":"Jie Han","orcid":"https://orcid.org/0000-0002-8849-4994"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jie Han","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, CANADA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, CANADA","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088690792","display_name":"Eugene Leung","orcid":null},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Eugene Leung","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, CANADA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, CANADA","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100358856","display_name":"Leibo Liu","orcid":"https://orcid.org/0000-0001-7548-4116"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Leibo Liu","raw_affiliation_strings":["Institute of Microelectronics, Beijing, China",", Institute of Microelectronics, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Beijing, China","institution_ids":["https://openalex.org/I4210119392"]},{"raw_affiliation_string":", Institute of Microelectronics, Beijing, China","institution_ids":["https://openalex.org/I4210119392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001979328","display_name":"Fabrizio Lombardi","orcid":"https://orcid.org/0000-0003-3152-3245"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fabrizio Lombardi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, MA, USA","Department of Electrical and Computer Engineering, Northeastern University,Boston,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, MA, USA","institution_ids":["https://openalex.org/I12912129"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University,Boston,USA","institution_ids":["https://openalex.org/I12912129"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.5222,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.93297003,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"23","issue":"8","first_page":"1562","last_page":"1566"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.8185268044471741},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.729810357093811},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.6457599997520447},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.635587215423584},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5977128744125366},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5869390964508057},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5375784039497375},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.5291997194290161},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5267091393470764},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5159233808517456},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5027866363525391},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47813618183135986},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4517008662223816},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4109698235988617},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3376404047012329},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2578169107437134},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22304090857505798},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17353808879852295},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.09513235092163086}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.8185268044471741},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.729810357093811},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.6457599997520447},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.635587215423584},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5977128744125366},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5869390964508057},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5375784039497375},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.5291997194290161},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5267091393470764},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5159233808517456},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5027866363525391},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47813618183135986},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4517008662223816},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4109698235988617},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3376404047012329},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2578169107437134},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22304090857505798},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17353808879852295},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.09513235092163086},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2341610","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2341610","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1968010872","https://openalex.org/W1978326660","https://openalex.org/W2018122835","https://openalex.org/W2071310017","https://openalex.org/W2104489073","https://openalex.org/W2126258474","https://openalex.org/W2153079001","https://openalex.org/W2153922221","https://openalex.org/W2154344146","https://openalex.org/W2157692642","https://openalex.org/W2158241730","https://openalex.org/W2163270290","https://openalex.org/W4229525459","https://openalex.org/W4243065018","https://openalex.org/W6630623413"],"related_works":["https://openalex.org/W2069145203","https://openalex.org/W2085176210","https://openalex.org/W1702800398","https://openalex.org/W2106889348","https://openalex.org/W2083793411","https://openalex.org/W2135500595","https://openalex.org/W2543766998","https://openalex.org/W573124066","https://openalex.org/W1969171031","https://openalex.org/W1592424226"],"abstract_inverted_index":{"Advances":[0],"in":[1,56,145,179],"CMOS":[2],"technology":[3],"have":[4,24],"made":[5],"digital":[6],"circuits":[7,152,184],"and":[8,111,122,158,185],"systems":[9],"very":[10,147,159],"sensitive":[11],"to":[12,48,68,94,165],"manufacturing":[13],"variations,":[14],"aging,":[15],"and/or":[16],"soft":[17],"errors.":[18],"Fault-tolerant":[19],"techniques":[20,143,178],"using":[21,126],"hardware":[22],"redundancy":[23,121],"been":[25],"extensively":[26],"investigated":[27],"for":[28,174],"improving":[29],"reliability.":[30],"Quadded":[31],"logic":[32,38,103],"(QL)":[33],"is":[34,92,109],"an":[35],"interwoven":[36,124],"redundant":[37],"technique":[39,86,108],"that":[40,87,133],"corrects":[41,73],"errors":[42,55,74],"by":[43],"switching":[44],"them":[45],"from":[46,162],"critical":[47],"subcritical":[49],"status;":[50],"however,":[51],"QL":[52,89],"cannot":[53],"correct":[54],"the":[57,77,140,146,180],"last":[58],"one":[59],"or":[60],"two":[61],"layers":[62],"of":[63,79,97,150,182],"a":[64,80,85,136,171],"circuit.":[65,81],"In":[66,82],"contrast":[67],"QL,":[69],"quadded":[70,102,105],"transistor":[71,106],"(QT)":[72],"while":[75],"performing":[76],"function":[78],"this":[83],"brief,":[84],"combines":[88],"with":[90,104,113,153],"QT":[91],"proposed":[93,101],"take":[95],"advantage":[96],"both":[98],"techniques.":[99],"The":[100],"(QLQT)":[107],"evaluated":[110],"compared":[112],"other":[114,141],"fault-tolerant":[115,142,177],"techniques,":[116],"such":[117],"as":[118],"triple":[119,123],"modular":[120],"redundancy,":[125],"stochastic":[127],"computational":[128],"models.":[129],"Simulation":[130],"results":[131,169],"show":[132],"QLQT":[134],"has":[135],"better":[137],"reliability":[138],"than":[139],"(except":[144],"restrictive":[148],"case":[149],"small":[151],"low":[154],"gate":[155],"error":[156],"rates":[157],"short":[160],"paths":[161],"primary":[163,166],"inputs":[164],"outputs).":[167],"These":[168],"provide":[170],"new":[172],"insight":[173],"implementing":[175],"efficient":[176],"design":[181],"reliable":[183],"systems.":[186]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":9},{"year":2017,"cited_by_count":8},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}