{"id":"https://openalex.org/W2078837501","doi":"https://doi.org/10.1109/tvlsi.2014.2341352","title":"High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost","display_name":"High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost","publication_year":2014,"publication_date":"2014-09-09","ids":{"openalex":"https://openalex.org/W2078837501","doi":"https://doi.org/10.1109/tvlsi.2014.2341352","mag":"2078837501"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2341352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2341352","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108674610","display_name":"Nobutaro Shibata","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Nobutaro Shibata","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, Atsugi, Japan",", NTT Microsystem Integration Laboratories, Atsugi, Japan"],"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, Atsugi, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":", NTT Microsystem Integration Laboratories, Atsugi, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110403350","display_name":"Yoshinori Gotoh","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yoshinori Gotoh","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, Atsugi, Japan",", NTT Microsystem Integration Laboratories, Atsugi, Japan"],"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, Atsugi, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":", NTT Microsystem Integration Laboratories, Atsugi, Japan","institution_ids":["https://openalex.org/I2251713219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108674610"],"corresponding_institution_ids":["https://openalex.org/I2251713219"],"apc_list":null,"apc_paid":null,"fwci":0.628,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.73990522,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"23","issue":"8","first_page":"1415","last_page":"1428"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6225247383117676},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.5831822752952576},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5782034993171692},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5776349902153015},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.523358941078186},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4879738688468933},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.46886497735977173},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4135449230670929},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.406075119972229},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3702681064605713},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36476099491119385},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.26991137862205505},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2696252465248108},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.25121352076530457}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6225247383117676},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.5831822752952576},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5782034993171692},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5776349902153015},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.523358941078186},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4879738688468933},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.46886497735977173},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4135449230670929},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.406075119972229},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3702681064605713},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36476099491119385},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.26991137862205505},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2696252465248108},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.25121352076530457},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2341352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2341352","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8100000023841858,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W436750969","https://openalex.org/W1527645624","https://openalex.org/W1533087512","https://openalex.org/W1632725962","https://openalex.org/W1844567777","https://openalex.org/W1982757128","https://openalex.org/W1997027527","https://openalex.org/W2001894083","https://openalex.org/W2003644260","https://openalex.org/W2030423646","https://openalex.org/W2032963257","https://openalex.org/W2052389663","https://openalex.org/W2071870540","https://openalex.org/W2078043934","https://openalex.org/W2096644804","https://openalex.org/W2098264411","https://openalex.org/W2109531912","https://openalex.org/W2118304747","https://openalex.org/W2121938580","https://openalex.org/W2126718299","https://openalex.org/W2128085968","https://openalex.org/W2131779457","https://openalex.org/W2137042751","https://openalex.org/W2142718365","https://openalex.org/W2184755715","https://openalex.org/W4242060669","https://openalex.org/W4250364519","https://openalex.org/W6650975361","https://openalex.org/W6658158987","https://openalex.org/W6663490211","https://openalex.org/W6674280908"],"related_works":["https://openalex.org/W2889102485","https://openalex.org/W2388299947","https://openalex.org/W2134697552","https://openalex.org/W2103645363","https://openalex.org/W2072989701","https://openalex.org/W4385831984","https://openalex.org/W3047211184","https://openalex.org/W2158494242","https://openalex.org/W1738647919","https://openalex.org/W2169589717"],"abstract_inverted_index":{"A":[0],"gate":[1],"array":[2],"has":[3],"a":[4,42,65,81,112,153,173,178,189,204,240,246,268,276,283,310],"great":[5],"advantage":[6],"in":[7,37,86,147,152],"that":[8],"the":[9,20,38,75,131,148,184,195,211,223,289,306],"extra":[10],"cost":[11],"required":[12,224],"for":[13,71,316],"customizing":[14],"VLSI":[15,45],"masks":[16],"is":[17,28,32,69,98,201,302,313],"low":[18,278],"and":[19,34,104,142,248,299,305],"lead":[21],"time":[22,292],"needed":[23,78],"to":[24,79,170,193,202,210,230,235],"obtain":[25],"an":[26,166,317],"ASIC":[27,39],"short.":[29],"Hence,":[30],"it":[31],"widely":[33],"generally":[35],"used":[36,70],"industry":[40],"as":[41,124],"major":[43],"semicustomized":[44],"design":[46],"methodology.":[47],"This":[48],"paper":[49],"presents":[50],"high-density":[51,242],"RAM/ROM":[52,82,135,270],"macros":[53],"using":[54,245,257],"memory-oriented":[55],"CMOS":[56,280],"gate-array":[57,269],"base":[58,149,156,161,259],"cells.":[59],"The":[60,95],"metatile":[61],"methodology":[62],"along":[63],"with":[64,267,275,286],"hierarchical":[66],"verification":[67,255],"technique":[68,200],"macro":[72,83,96,113,271],"design;":[73],"all":[74],"interconnection":[76],"wires":[77],"generate":[80],"are":[84,114,119,145,261,265],"installed":[85],"each":[87],"physical":[88],"leaf":[89],"cell":[90,168],"by":[91],"way":[92],"of":[93,134,216,296,320],"preparation.":[94],"size":[97],"configurable":[99],"regarding":[100],"both":[101],"word":[102],"count":[103],"bit":[105],"width.":[106],"Moreover,":[107],"back":[108],"annotations":[109],"after":[110],"generating":[111],"not":[115],"necessary":[116],"because":[117],"there":[118],"no":[120],"unknown":[121],"factors":[122],"such":[123],"parasitic":[125],"resistance":[126],"and/or":[127],"capacitance.":[128],"To":[129],"reduce":[130],"power":[132],"consumption":[133],"macros,":[136],"six":[137],"narrow-channel":[138],"MOSFETs":[139],"(two":[140],"pMOSs":[141],"four":[143],"nMOSs)":[144],"prepared":[146],"cell,":[150,162,176,186],"resulting":[151],"new":[154,205,241],"10-transistor-type":[155],"cell.":[157],"Using":[158],"one":[159],"single":[160],"we":[163,187,219,238],"can":[164],"implement":[165],"SRAM":[167,285],"(up":[169],"two":[171],"ports),":[172],"4-bit":[174],"ROM":[175,185],"or":[177],"2-input":[179],"logic":[180,250],"gate.":[181],"When":[182],"designing":[183],"adopt":[188],"double-rail":[190],"bitline":[191,196,226],"scheme":[192],"shorten":[194],"delay.":[197],"Another":[198],"high-speed":[199],"use":[203],"current-mirror":[206],"sense":[207],"amplifier.":[208],"Owing":[209],"high":[212],"sensitivity":[213],"(47":[214],"mV)":[215],"this":[217],"amplifier,":[218],"have":[220],"successfully":[221],"reduced":[222],"read":[225],"signal":[227],"from":[228],"300":[229],"100":[231],"mVpp.":[232],"With":[233,282],"regards":[234],"layout":[236],"techniques,":[237],"propose":[239],"address":[243,290],"decoder":[244],"subdecoder":[247],"complex":[249],"gates.":[251],"In":[252],"addition,":[253],"some":[254],"techniques":[256,264],"phantom":[258],"cells":[260],"devised.":[262],"These":[263],"confirmed":[266],"test":[272],"chip":[273],"fabricated":[274],"0.6-\u03bcm":[277],"cost,":[279],"process.":[281],"two-port":[284],"256":[287],"cells/bitline,":[288],"access":[291],"under":[293],"typical":[294],"conditions":[295],"3.3":[297],"V":[298],"25":[300],"\u00b0C":[301],"7.125":[303],"ns":[304],"power-supply":[307],"current":[308],"at":[309],"40-MHz":[311],"operation":[312],"3.8":[314],"mA":[315],"I/O-data":[318],"width":[319],"1":[321],"bit.":[322]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
