{"id":"https://openalex.org/W1994828163","doi":"https://doi.org/10.1109/tvlsi.2014.2338309","title":"An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability","display_name":"An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability","publication_year":2014,"publication_date":"2014-08-12","ids":{"openalex":"https://openalex.org/W1994828163","doi":"https://doi.org/10.1109/tvlsi.2014.2338309","mag":"1994828163"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2338309","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2338309","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084504231","display_name":"Chi-Heng Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chi-Heng Yang","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","[Department of Electronics EngineeringInstitute of Electronics, National Chiao Tung University, Hsinchu, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electronics EngineeringInstitute of Electronics, National Chiao Tung University, Hsinchu, Taiwan]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102164038","display_name":"Yi-Min Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Min Lin","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","[Department of Electronics EngineeringInstitute of Electronics, National Chiao Tung University, Hsinchu, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electronics EngineeringInstitute of Electronics, National Chiao Tung University, Hsinchu, Taiwan]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074752759","display_name":"Hsie-Chia Chang","orcid":"https://orcid.org/0000-0002-0525-8129"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hsie-Chia Chang","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","[Department of Electronics EngineeringInstitute of Electronics, National Chiao Tung University, Hsinchu, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electronics EngineeringInstitute of Electronics, National Chiao Tung University, Hsinchu, Taiwan]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101838014","display_name":"Chen\u2010Yi Lee","orcid":"https://orcid.org/0000-0002-6795-0874"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chen-Yi Lee","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","[Department of Electronics EngineeringInstitute of Electronics, National Chiao Tung University, Hsinchu, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electronics EngineeringInstitute of Electronics, National Chiao Tung University, Hsinchu, Taiwan]","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3599,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.6517883,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"23","issue":"7","first_page":"1235","last_page":"1244"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bch-code","display_name":"BCH code","score":0.7651312947273254},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7446671724319458},{"id":"https://openalex.org/keywords/gate-count","display_name":"Gate count","score":0.6598575711250305},{"id":"https://openalex.org/keywords/codec","display_name":"Codec","score":0.6313732862472534},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5901350975036621},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.582079291343689},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.544640064239502},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.5000982284545898},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.48596274852752686},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.456430584192276},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42686864733695984},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35191747546195984},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.34756481647491455},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.34556907415390015},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3320190906524658},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.18032518029212952},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17658060789108276}],"concepts":[{"id":"https://openalex.org/C42276685","wikidata":"https://www.wikidata.org/wiki/Q795705","display_name":"BCH code","level":3,"score":0.7651312947273254},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7446671724319458},{"id":"https://openalex.org/C2777892113","wikidata":"https://www.wikidata.org/wiki/Q5527005","display_name":"Gate count","level":2,"score":0.6598575711250305},{"id":"https://openalex.org/C161765866","wikidata":"https://www.wikidata.org/wiki/Q184748","display_name":"Codec","level":2,"score":0.6313732862472534},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5901350975036621},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.582079291343689},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.544640064239502},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.5000982284545898},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48596274852752686},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.456430584192276},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42686864733695984},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35191747546195984},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.34756481647491455},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.34556907415390015},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3320190906524658},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.18032518029212952},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17658060789108276},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2338309","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2338309","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1593683169","https://openalex.org/W1738875156","https://openalex.org/W1766888123","https://openalex.org/W1990176214","https://openalex.org/W2041989673","https://openalex.org/W2053979825","https://openalex.org/W2067525510","https://openalex.org/W2083774980","https://openalex.org/W2091668647","https://openalex.org/W2103879481","https://openalex.org/W2109236154","https://openalex.org/W2110933153","https://openalex.org/W2114512042","https://openalex.org/W2125099110","https://openalex.org/W2129821171","https://openalex.org/W2148575324","https://openalex.org/W2167767753","https://openalex.org/W2199682189","https://openalex.org/W2478884216","https://openalex.org/W2545639319","https://openalex.org/W2942537621","https://openalex.org/W4251178606","https://openalex.org/W6661617524","https://openalex.org/W6663996228","https://openalex.org/W6673574363","https://openalex.org/W6679248497","https://openalex.org/W6729462964"],"related_works":["https://openalex.org/W2912502034","https://openalex.org/W3028734320","https://openalex.org/W2506979107","https://openalex.org/W4239727543","https://openalex.org/W2612882049","https://openalex.org/W4311168466","https://openalex.org/W2951146762","https://openalex.org/W2284101512","https://openalex.org/W1598105334","https://openalex.org/W2116533108"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"area-efficient":[4],"architecture":[5],"of":[6],"arbitrary":[7],"error":[8,42],"correction":[9],"Bose-Chaudhuri-Hocquenghem":[10],"codec":[11],"for":[12,58],"NAND":[13],"flash":[14],"memory.":[15],"By":[16],"factorizing":[17],"the":[18,53,70],"generator":[19],"polynomial":[20],"into":[21],"several":[22],"minimal":[23,33],"polynomials":[24],"and":[25,55],"utilizing":[26],"linear":[27],"feedback":[28],"shift":[29],"registers":[30],"based":[31],"on":[32],"polynomials,":[34],"our":[35],"reconfigurable":[36],"design":[37,88],"cannot":[38],"only":[39],"support":[40],"multiple":[41],"correcting":[43],"capabilities":[44],"at":[45],"a":[46],"few":[47],"extra":[48],"cost,":[49],"but":[50],"also":[51],"merge":[52],"encoder":[54],"syndrome":[56],"calculator":[57],"efficiently":[59],"reducing":[60],"hardware":[61],"complexity.":[62],"After":[63],"being":[64],"implemented":[65],"in":[66],"CMOS":[67],"65-nm":[68],"technology,":[69],"test":[71],"chip":[72],"supporting":[73,89],"t":[74,90],"=":[75,91],"1-24":[76],"bits":[77,93],"can":[78,94],"achieve":[79],"1.33-Gb/s":[80],"measured":[81],"throughput":[82,98],"with":[83,99],"73k":[84],"gate-count":[85],"while":[86],"another":[87],"60-84":[92],"provide":[95],"1.60-Gb/s":[96],"synthesized":[97],"168.6k":[100],"gate-count.":[101]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
