{"id":"https://openalex.org/W2153469416","doi":"https://doi.org/10.1109/tvlsi.2014.2320912","title":"Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs","display_name":"Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs","publication_year":2014,"publication_date":"2014-05-19","ids":{"openalex":"https://openalex.org/W2153469416","doi":"https://doi.org/10.1109/tvlsi.2014.2320912","mag":"2153469416"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2320912","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2320912","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075493693","display_name":"Supriya Karmakar","orcid":"https://orcid.org/0000-0002-2761-4382"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Supriya Karmakar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Connecticut, CT, Storrs, USA","Intel Corporation, OR, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Connecticut, CT, Storrs, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"Intel Corporation, OR, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082629462","display_name":"John A. Chandy","orcid":"https://orcid.org/0000-0003-3449-3205"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John A. Chandy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Connecticut, CT, Storrs, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Connecticut, CT, Storrs, USA","institution_ids":["https://openalex.org/I140172145"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061990217","display_name":"F. Jain","orcid":"https://orcid.org/0000-0003-3961-6665"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Faquir C. Jain","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Connecticut, CT, Storrs, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Connecticut, CT, Storrs, USA","institution_ids":["https://openalex.org/I140172145"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6388,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.75165094,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"23","issue":"4","first_page":"609","last_page":"618"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10382","display_name":"Quantum and electron transport phenomena","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.738813579082489},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6984270811080933},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6769092679023743},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6088552474975586},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.585580050945282},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5853488445281982},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5700073838233948},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5234398245811462},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.5050769448280334},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.462698757648468},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.42973899841308594},{"id":"https://openalex.org/keywords/nor-logic","display_name":"NOR logic","score":0.42351508140563965},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4094802141189575},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.394153356552124},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.36381661891937256},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33540546894073486},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.2956753969192505},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.24907267093658447},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21614432334899902},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.17341569066047668}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.738813579082489},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6984270811080933},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6769092679023743},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6088552474975586},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.585580050945282},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5853488445281982},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5700073838233948},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5234398245811462},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5050769448280334},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.462698757648468},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.42973899841308594},{"id":"https://openalex.org/C165862026","wikidata":"https://www.wikidata.org/wiki/Q670372","display_name":"NOR logic","level":5,"score":0.42351508140563965},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4094802141189575},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.394153356552124},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.36381661891937256},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33540546894073486},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2956753969192505},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.24907267093658447},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21614432334899902},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.17341569066047668}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2320912","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2320912","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1548212700","https://openalex.org/W1570722307","https://openalex.org/W1977169897","https://openalex.org/W1978985788","https://openalex.org/W1983015996","https://openalex.org/W1983187319","https://openalex.org/W2001894083","https://openalex.org/W2015209061","https://openalex.org/W2044949727","https://openalex.org/W2046320024","https://openalex.org/W2069870201","https://openalex.org/W2092254501","https://openalex.org/W2105427723","https://openalex.org/W2117453169","https://openalex.org/W2129736765","https://openalex.org/W2147487316","https://openalex.org/W2148720570","https://openalex.org/W6650975361","https://openalex.org/W6677609719"],"related_works":["https://openalex.org/W2151687972","https://openalex.org/W4214735176","https://openalex.org/W2502492371","https://openalex.org/W1017999001","https://openalex.org/W4391079636","https://openalex.org/W2774143721","https://openalex.org/W1759507974","https://openalex.org/W2044930572","https://openalex.org/W1576731273","https://openalex.org/W2181523649"],"abstract_inverted_index":{"The":[0],"spatial":[1],"wave-function":[2],"switched":[3],"field-effect":[4],"transistor":[5],"(SWSFET)":[6],"has":[7],"two":[8,77],"or":[9],"three":[10],"low":[11],"bandgap":[12],"quantum":[13],"well":[14],"channels":[15],"that":[16],"can":[17],"conduct":[18],"carrier":[19,68],"flow":[20],"from":[21],"source":[22],"to":[23,35,70,92],"drain":[24],"of":[25,29,52,58,66],"the":[26,49,56,71],"SWSFET.":[27],"Because":[28],"this":[30,45],"property,":[31],"SWSFETs":[32],"are":[33],"useful":[34],"implement":[36,93],"different":[37],"multivalued":[38],"logic":[39,80,96,110],"with":[40],"reduced":[41],"device":[42],"count.":[43],"In":[44],"paper,":[46],"we":[47],"introduce":[48],"circuit":[50],"model":[51],"a":[53,59],"SWSFET":[54],"and":[55,85,87,103],"design":[57],"unipolar":[60,79,95,109],"inverter":[61],"where":[62],"only":[63],"one":[64],"kind":[65],"charge":[67],"contributes":[69],"current":[72],"flow.":[73],"We":[74,98],"also":[75,99],"simulate":[76,100],"input":[78],"gates":[81],"such":[82],"as":[83],"NAND":[84],"NOR":[86,101],"demonstrate":[88],"their":[89],"universal":[90],"property":[91],"other":[94],"gates.":[97,111],"gate":[102],"full":[104],"adder":[105],"circuits":[106],"based":[107],"on":[108]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}