{"id":"https://openalex.org/W2044230919","doi":"https://doi.org/10.1109/tvlsi.2014.2313131","title":"Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line","display_name":"Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line","publication_year":2014,"publication_date":"2014-04-08","ids":{"openalex":"https://openalex.org/W2044230919","doi":"https://doi.org/10.1109/tvlsi.2014.2313131","mag":"2044230919"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2313131","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2313131","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101721828","display_name":"Chia-Yu Yao","orcid":"https://orcid.org/0000-0001-9771-041X"},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Yu Yao","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","[Department of Electrical Engineering, National-Taiwan University of Science and Technology, Taipei, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]},{"raw_affiliation_string":"[Department of Electrical Engineering, National-Taiwan University of Science and Technology, Taipei, Taiwan]","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062367921","display_name":"Yung-Hsiang Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Hsiang Ho","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","[Department of Electrical Engineering, National-Taiwan University of Science and Technology, Taipei, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]},{"raw_affiliation_string":"[Department of Electrical Engineering, National-Taiwan University of Science and Technology, Taipei, Taiwan]","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039725120","display_name":"Yi-Yao Chiu","orcid":null},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Yao Chiu","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","[Department of Electrical Engineering, National-Taiwan University of Science and Technology, Taipei, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]},{"raw_affiliation_string":"[Department of Electrical Engineering, National-Taiwan University of Science and Technology, Taipei, Taiwan]","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110211948","display_name":"Rong-Jyi Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148979","display_name":"MediaTek (Taiwan)","ror":"https://ror.org/05g9jck81","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210148979"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Rong-Jyi Yang","raw_affiliation_strings":["MediaTek Inc., Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MediaTek Inc., Taipei, Taiwan","institution_ids":["https://openalex.org/I4210148979"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.0719,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.884173,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"23","issue":"3","first_page":"567","last_page":"574"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8225706815719604},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.6686356067657471},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5578591823577881},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5447652339935303},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5311305522918701},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5200918912887573},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5144779682159424},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.502347469329834},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5010292530059814},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4914661645889282},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.460125207901001},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4166114330291748},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4142317771911621},{"id":"https://openalex.org/keywords/phase-frequency-detector","display_name":"Phase frequency detector","score":0.4121990203857422},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.32992345094680786},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3222430944442749},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.291901171207428},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2226889431476593},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.1088600754737854},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.09320709109306335},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09306660294532776},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.07918965816497803}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8225706815719604},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.6686356067657471},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5578591823577881},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5447652339935303},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5311305522918701},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5200918912887573},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5144779682159424},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.502347469329834},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5010292530059814},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4914661645889282},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.460125207901001},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4166114330291748},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4142317771911621},{"id":"https://openalex.org/C2776158855","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase frequency detector","level":5,"score":0.4121990203857422},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.32992345094680786},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3222430944442749},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.291901171207428},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2226889431476593},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.1088600754737854},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.09320709109306335},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09306660294532776},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.07918965816497803}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2313131","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2313131","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[{"id":"https://openalex.org/G2651083385","display_name":null,"funder_award_id":"101-2221-E-011-168","funder_id":"https://openalex.org/F4320321040","funder_display_name":"National Science Council"}],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1997826936","https://openalex.org/W2002187871","https://openalex.org/W2009275112","https://openalex.org/W2019109746","https://openalex.org/W2111053525","https://openalex.org/W2117599119","https://openalex.org/W2124390946","https://openalex.org/W2126227985","https://openalex.org/W2133294020","https://openalex.org/W2141594064","https://openalex.org/W2144572765","https://openalex.org/W2153119050","https://openalex.org/W6651009612","https://openalex.org/W6655305116"],"related_works":["https://openalex.org/W2124909075","https://openalex.org/W2169622190","https://openalex.org/W1607003253","https://openalex.org/W2117541676","https://openalex.org/W2224788396","https://openalex.org/W2169618112","https://openalex.org/W2118205354","https://openalex.org/W2151256709","https://openalex.org/W4238381000","https://openalex.org/W1691859631"],"abstract_inverted_index":{"Previous":[0],"high-performance":[1],"delay-locked":[2],"loops":[3],"(DLLs)":[4],"were":[5],"designed":[6],"in":[7,44,96],"a":[8,45,58,97],"full-custom":[9],"design":[10,47],"flow":[11],"that":[12,79],"is":[13,76,127,142,158,165],"labor-intensive.":[14],"Most":[15],"of":[16,23,29,57,104,139],"those":[17],"DLLs":[18],"require":[19],"tens":[20],"to":[21,26,64],"hundreds":[22],"clock":[24,31,59,147,173],"cycles":[25,43],"achieve":[27],"synchronization":[28],"the":[30,55,70,90,101,111,114,121,130,140,162],"signal.":[32],"This":[33,87],"paper":[34,88],"presents":[35],"an":[36],"all-digital":[37],"DLL":[38,83],"(ADDLL)":[39],"with":[40],"constant":[41,81],"acquisition":[42],"cell-based":[46],"flow.":[48],"The":[49,124,135,155],"proposed":[50,115],"ADDLL":[51,116,125],"circuit":[52],"can":[53,85,118],"acquire":[54],"phase":[56],"signal":[60],"from":[61],"60-MHz":[62],"frequency":[63,148],"1.2-GHz":[65,146,172],"frequency.":[66,174],"In":[67],"this":[68],"paper,":[69],"digitally":[71],"controlled":[72],"delay":[73,94,102],"line":[74],"(DCDL)":[75],"resettable":[77],"such":[78],"our":[80,105],"acquisition-cycle":[82],"algorithm":[84,117],"apply.":[86],"realizes":[89],"DCDL":[91,106],"using":[92,129],"lattice":[93],"units":[95],"linear":[98],"manner,":[99],"so":[100],"profile":[103],"shows":[107],"good":[108],"linearity.":[109],"On":[110],"other":[112],"hand,":[113],"effectively":[119],"eliminate":[120],"harmonic":[122],"lock.":[123],"chip":[126,141],"implemented":[128],"Artisan-TSMC-0.18-\u03bcm":[131],"CMOS":[132],"cell":[133],"library.":[134],"measured":[136,170],"power":[137],"consumption":[138],"16.2":[143],"mW":[144],"at":[145,150,171],"and":[149,161],"1.8":[151],"V":[152],"supply":[153],"voltage.":[154],"rms":[156],"jitter":[157,164],"1.63":[159],"ps":[160],"peak-to-peak":[163],"12.8":[166],"ps.":[167],"Both":[168],"are":[169]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
