{"id":"https://openalex.org/W2048864063","doi":"https://doi.org/10.1109/tvlsi.2014.2311798","title":"Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache","display_name":"Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache","publication_year":2014,"publication_date":"2014-03-31","ids":{"openalex":"https://openalex.org/W2048864063","doi":"https://doi.org/10.1109/tvlsi.2014.2311798","mag":"2048864063"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2014.2311798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2311798","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000758083","display_name":"Seunghan Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seunghan Lee","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","Department of Electrical Engineering, Korea Advanced Institute of Science and Technology Daejeon Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology Daejeon Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037212268","display_name":"Kyungsu Kang","orcid":"https://orcid.org/0000-0002-6955-578X"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyungsu Kang","raw_affiliation_strings":["Samsung Electronics, Hwaseongsi, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Electronics, Hwaseongsi, Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101611981","display_name":"Chong\u2010Min Kyung","orcid":"https://orcid.org/0000-0002-3959-9714"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Chong-Min Kyung","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","Department of Electrical Engineering, Korea Advanced Institute of Science and Technology Daejeon Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology Daejeon Korea","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.5755,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.83138692,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"23","issue":"3","first_page":"520","last_page":"533"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6969665288925171},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.677384614944458},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6652642488479614},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5577940344810486},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.5351855158805847},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5142245292663574},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44590747356414795},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.43198007345199585},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42735961079597473},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.42572250962257385},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2575540244579315},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.10191479325294495}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6969665288925171},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.677384614944458},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6652642488479614},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5577940344810486},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.5351855158805847},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5142245292663574},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44590747356414795},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.43198007345199585},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42735961079597473},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.42572250962257385},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2575540244579315},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.10191479325294495},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2014.2311798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2014.2311798","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":55,"referenced_works":["https://openalex.org/W1569032152","https://openalex.org/W1839868653","https://openalex.org/W1972372570","https://openalex.org/W1973459854","https://openalex.org/W2003730986","https://openalex.org/W2010202670","https://openalex.org/W2022186439","https://openalex.org/W2024463451","https://openalex.org/W2055170852","https://openalex.org/W2061758778","https://openalex.org/W2069277547","https://openalex.org/W2084007230","https://openalex.org/W2096867266","https://openalex.org/W2101308451","https://openalex.org/W2102449048","https://openalex.org/W2102694790","https://openalex.org/W2104500100","https://openalex.org/W2105768042","https://openalex.org/W2108453702","https://openalex.org/W2109373376","https://openalex.org/W2111538921","https://openalex.org/W2113167168","https://openalex.org/W2116283643","https://openalex.org/W2119190255","https://openalex.org/W2126339718","https://openalex.org/W2129960401","https://openalex.org/W2131413854","https://openalex.org/W2141923369","https://openalex.org/W2142322859","https://openalex.org/W2143807959","https://openalex.org/W2144005128","https://openalex.org/W2144691765","https://openalex.org/W2149809112","https://openalex.org/W2159450369","https://openalex.org/W2160024982","https://openalex.org/W2161364792","https://openalex.org/W2163083688","https://openalex.org/W2164705534","https://openalex.org/W2168473468","https://openalex.org/W2170382128","https://openalex.org/W2171148960","https://openalex.org/W2174102096","https://openalex.org/W2543205889","https://openalex.org/W3101347303","https://openalex.org/W3139689176","https://openalex.org/W3141627443","https://openalex.org/W3142248664","https://openalex.org/W4230996008","https://openalex.org/W6638886375","https://openalex.org/W6656041504","https://openalex.org/W6674416589","https://openalex.org/W6676125783","https://openalex.org/W6676823070","https://openalex.org/W6677142978","https://openalex.org/W6729029536"],"related_works":["https://openalex.org/W2012518269","https://openalex.org/W2086718556","https://openalex.org/W2404820046","https://openalex.org/W2167303720","https://openalex.org/W2061075966","https://openalex.org/W2146079099","https://openalex.org/W2066160958","https://openalex.org/W1965891727","https://openalex.org/W218254741","https://openalex.org/W2109715593"],"abstract_inverted_index":{"Nonvolatile":[0],"memory":[1,37],"such":[2,112],"as":[3,52,113],"magnetic":[4],"RAM":[5],"(MRAM)":[6],"offers":[7,152],"high":[8,22,70],"cell":[9],"density":[10,72],"and":[11,21,41,73,119,125,134,161],"low":[12],"leakage":[13],"power":[14,71,117],"while":[15],"suffering":[16],"from":[17],"long":[18],"write":[19,23],"latency":[20],"energy,":[24],"compared":[25,169],"with":[26,97,122,145,170,175],"SRAM.":[27],"3-D":[28,78,99,147,176],"integration":[29],"technology":[30,65],"using":[31],"through-silicon":[32],"vias":[33],"enables":[34],"stacking":[35],"disparate":[36],"technologies":[38],"(e.g.,":[39],"SRAM":[40],"MRAM)":[42],"together":[43],"onto":[44],"chip-multiprocessors":[45],"(CMPs).":[46],"The":[47,105],"use":[48],"of":[49,59,128],"hybrid":[50,101,149],"memories":[51],"an":[53],"on-chip":[54],"cache":[55,110,151],"can":[56],"take":[57],"advantage":[58],"the":[60,68,98,141,146],"best":[61],"characteristics":[62],"that":[63,140],"each":[64],"offers.":[66],"However,":[67],"inherent":[69],"heat":[74],"removal":[75],"limitation":[76],"in":[77,131],"integrated":[79],"circuits":[80],"may":[81],"incur":[82],"temperature-related":[83],"problems.":[84],"In":[85],"this":[86],"paper,":[87],"we":[88],"propose":[89],"a":[90,132],"runtime":[91,143],"thermal":[92,172],"management":[93,111,173],"method":[94,107,144],"for":[95],"CMPs":[96],"stacked":[100,148,177],"SRAM/MRAM":[102],"L2":[103,150,179],"cache.":[104,180],"proposed":[106,142],"combines":[108],"dynamic":[109,123],"resource":[114],"allocation,":[115],"way-based":[116],"gating,":[118],"data":[120],"migration":[121],"voltage":[124],"frequency":[126],"scaling":[127],"processing":[129],"cores":[130],"temperature-":[133],"energy-aware":[135],"manner.":[136],"Experimental":[137],"results":[138],"show":[139],"up":[153],"to":[154],"107.37%":[155],"(55.28%":[156],"on":[157,164],"average)":[158,165],"performance":[159],"improvement":[160,168],"88.47%":[162],"(47.65%":[163],"energy":[166],"efficiency":[167],"existing":[171],"methods":[174],"SRAM-based":[178]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}