{"id":"https://openalex.org/W2058732093","doi":"https://doi.org/10.1109/tvlsi.2013.2296791","title":"A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA","display_name":"A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA","publication_year":2014,"publication_date":"2014-01-31","ids":{"openalex":"https://openalex.org/W2058732093","doi":"https://doi.org/10.1109/tvlsi.2013.2296791","mag":"2058732093"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2013.2296791","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2296791","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102891205","display_name":"Jianfeng Zhu","orcid":"https://orcid.org/0000-0002-0485-8034"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianfeng Zhu","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102144520","display_name":"Liyang Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liyang Pan","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074874958","display_name":"Yaru Yan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yaru Yan","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110053681","display_name":"Dong Wu","orcid":"https://orcid.org/0009-0005-3376-2057"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dong Wu","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101553403","display_name":"Hu He","orcid":"https://orcid.org/0000-0003-3239-430X"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hu He","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5223,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.7184625,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"22","issue":"12","first_page":"2629","last_page":"2634"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7039477229118347},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.5865610241889954},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5627817511558533},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.5146359205245972},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5118831396102905},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.49103808403015137},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4631160497665405},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4379793703556061},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42880675196647644},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4277419447898865},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.4262255132198334},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34704726934432983},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3314167857170105},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3304412364959717},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2990420460700989},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24796253442764282},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20697370171546936},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.16642731428146362},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14135485887527466}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7039477229118347},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5865610241889954},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5627817511558533},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.5146359205245972},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5118831396102905},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.49103808403015137},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4631160497665405},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4379793703556061},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42880675196647644},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4277419447898865},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.4262255132198334},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34704726934432983},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3314167857170105},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3304412364959717},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2990420460700989},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24796253442764282},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20697370171546936},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.16642731428146362},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14135485887527466},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2013.2296791","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2296791","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8199999928474426,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G2565691279","display_name":null,"funder_award_id":"2011CBA00602","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"}],"funders":[{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1537216112","https://openalex.org/W1557877906","https://openalex.org/W1719300925","https://openalex.org/W1984176385","https://openalex.org/W1997742530","https://openalex.org/W2035847677","https://openalex.org/W2082928686","https://openalex.org/W2113992532","https://openalex.org/W2118513740","https://openalex.org/W2128409238","https://openalex.org/W2131314867","https://openalex.org/W2138840350","https://openalex.org/W2150951913","https://openalex.org/W2152391630","https://openalex.org/W2159142998","https://openalex.org/W3103339143","https://openalex.org/W6633444049","https://openalex.org/W6637449779"],"related_works":["https://openalex.org/W2014165129","https://openalex.org/W2367348190","https://openalex.org/W594316872","https://openalex.org/W2831860248","https://openalex.org/W2367794224","https://openalex.org/W2072850836","https://openalex.org/W2017163657","https://openalex.org/W1968650434","https://openalex.org/W2105610663","https://openalex.org/W1996607072"],"abstract_inverted_index":{"Dual":[0],"supply":[1],"voltage":[2,21,153],"was":[3,28,95],"a":[4,39,98,159],"mature":[5],"method":[6,111,143,165],"to":[7,30,45],"reduce":[8],"the":[9,18,47,65,72,76,109,133,151],"dynamic":[10],"power":[11,41,125,164],"of":[12,69,75],"specific":[13],"and":[14,17,71,92,161],"programmable":[15],"circuits,":[16],"unsettled":[19],"low":[20,163],"level":[22],"(V":[23],"<sub":[24,50,117],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[25,51,118],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">L</sub>":[26,52,119],")":[27],"proved":[29],"have":[31],"impact":[32],"on":[33,64,97],"its":[34],"effect.":[35],"In":[36],"this":[37],"paper,":[38],"circuit-level":[40],"model":[42,60,101],"is":[43,61,128,138,144,158],"developed":[44],"estimate":[46],"optimal":[48],"V":[49,116],"fast":[53],"for":[54,120,166],"field-programmable":[55,167],"gate":[56],"array":[57],"(FPGA).":[58],"The":[59,105,123],"mainly":[62],"based":[63],"path":[66,88],"delay":[67,73],"distribution":[68],"applications":[70],"function":[74],"integrated":[77],"circuit":[78],"technology.":[79],"It":[80,148],"can":[81],"also":[82],"count":[83],"minor":[84],"factors,":[85],"such":[86],"as":[87],"overlap,":[89],"transition":[90],"density,":[91],"capacitance.":[93],"Experiment":[94],"conducted":[96],"90-nm":[99],"FPGA":[100],"using":[102],"MCNC":[103],"benchmark.":[104],"results":[106],"showed":[107],"that":[108,150],"proposed":[110],"could":[112],"generate":[113],"near":[114],"optimum":[115],"most":[121],"benchmarks.":[122],"best":[124],"reduction":[126],"ratio":[127],"only":[129],"5.6%":[130],"less":[131],"than":[132],"gate-level":[134],"heuristic":[135],"method,":[136],"which":[137],"relatively":[139],"precise,":[140],"but":[141],"our":[142],"~100-10000":[145],"times":[146],"faster.":[147],"implies":[149],"dual":[152],"design":[154],"with":[155],"variable":[156],"VL":[157],"possible":[160],"promising":[162],"devices.":[168]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}