{"id":"https://openalex.org/W2091187076","doi":"https://doi.org/10.1109/tvlsi.2013.2290102","title":"A Configurable Monitoring Infrastructure for NoC-Based Architectures","display_name":"A Configurable Monitoring Infrastructure for NoC-Based Architectures","publication_year":2014,"publication_date":"2014-01-31","ids":{"openalex":"https://openalex.org/W2091187076","doi":"https://doi.org/10.1109/tvlsi.2013.2290102","mag":"2091187076"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2013.2290102","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2290102","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039264220","display_name":"Leandro Fiorin","orcid":"https://orcid.org/0000-0001-7069-9484"},"institutions":[{"id":"https://openalex.org/I922237871","display_name":"Netherlands Institute for Radio Astronomy","ror":"https://ror.org/000k1q888","country_code":"NL","type":"funder","lineage":["https://openalex.org/I2800991832","https://openalex.org/I922237871"]},{"id":"https://openalex.org/I57201433","display_name":"Universit\u00e0 della Svizzera italiana","ror":"https://ror.org/03c4atk17","country_code":"CH","type":"education","lineage":["https://openalex.org/I57201433"]}],"countries":["CH","NL"],"is_corresponding":true,"raw_author_name":"Leandro Fiorin","raw_affiliation_strings":["Advanced Learning and Research Institute, University of Lugano, Lugano, Switzerland","IBM Research\u2014ASTRON & IBM Center for Exascale Technology, Dwingeloo, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Advanced Learning and Research Institute, University of Lugano, Lugano, Switzerland","institution_ids":["https://openalex.org/I57201433"]},{"raw_affiliation_string":"IBM Research\u2014ASTRON & IBM Center for Exascale Technology, Dwingeloo, The Netherlands","institution_ids":["https://openalex.org/I922237871"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077005193","display_name":"Gianluca Palermo","orcid":"https://orcid.org/0000-0001-7955-8012"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Palermo","raw_affiliation_strings":["Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031461662","display_name":"Cristina Silvano","orcid":"https://orcid.org/0000-0003-1668-0883"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Cristina Silvano","raw_affiliation_strings":["Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5039264220"],"corresponding_institution_ids":["https://openalex.org/I57201433","https://openalex.org/I922237871"],"apc_list":null,"apc_paid":null,"fwci":0.36767639,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.68177656,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"22","issue":"11","first_page":"2438","last_page":"2442"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8652823567390442},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7598423957824707},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6829535961151123},{"id":"https://openalex.org/keywords/profiling","display_name":"Profiling (computer programming)","score":0.6822603940963745},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6622198820114136},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5884475708007812},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5754351615905762},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5743040442466736},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.508136510848999},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.49929285049438477},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.4160388112068176},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32818493247032166},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1976018249988556}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8652823567390442},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7598423957824707},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6829535961151123},{"id":"https://openalex.org/C187191949","wikidata":"https://www.wikidata.org/wiki/Q1138496","display_name":"Profiling (computer programming)","level":2,"score":0.6822603940963745},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6622198820114136},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5884475708007812},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5754351615905762},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5743040442466736},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.508136510848999},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.49929285049438477},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.4160388112068176},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32818493247032166},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1976018249988556},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2013.2290102","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2290102","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:re.public.polimi.it:11311/823930","is_oa":false,"landing_page_url":"http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6680709","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6399999856948853,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1582835330","https://openalex.org/W1630564764","https://openalex.org/W2030756078","https://openalex.org/W2054302810","https://openalex.org/W2084588639","https://openalex.org/W2093411808","https://openalex.org/W2121283714","https://openalex.org/W2127140660","https://openalex.org/W2148048063","https://openalex.org/W2148960378","https://openalex.org/W2168930811","https://openalex.org/W2540784783","https://openalex.org/W3143338891","https://openalex.org/W4254247376","https://openalex.org/W6634901851"],"related_works":["https://openalex.org/W2059759476","https://openalex.org/W1618604010","https://openalex.org/W2114320580","https://openalex.org/W4212932124","https://openalex.org/W2068239131","https://openalex.org/W2388672758","https://openalex.org/W2135981148","https://openalex.org/W2754086592","https://openalex.org/W1969623596","https://openalex.org/W2144357574"],"abstract_inverted_index":{"In":[0],"this":[1],"brief,":[2],"we":[3],"propose":[4],"a":[5,47],"monitoring":[6,54,87],"architecture":[7,99],"for":[8,15,53,63,74,100],"networks-on-chip":[9],"that":[10,56],"provides":[11],"system":[12,26,68],"information":[13,55,106],"useful":[14],"designers":[16],"to":[17],"efficiently":[18],"exploit,":[19],"at":[20,61,71],"design":[21,43,84],"time":[22,73],"and":[23,42,70,76,96,103],"run-time,":[24],"the":[25,36,39,83,86,91,105],"resources":[27],"available":[28],"in":[29,67],"multiprocessor":[30],"system-on-chip":[31],"platforms.":[32],"We":[33],"focus":[34],"on":[35],"analysis":[37],"of":[38,45,78,85],"architectural":[40],"details":[41],"challenges":[44],"such":[46],"system,":[48],"by":[49,94],"describing":[50],"powerful":[51],"tools":[52],"can":[57],"be":[58],"used":[59],"both":[60],"run-time":[62],"detecting":[64],"dynamic":[65],"changes":[66],"behavior":[69],"post-execution":[72],"debugging":[75],"profiling":[77],"applications.":[79],"This":[80],"brief":[81],"describes":[82],"probes,":[88],"together":[89],"with":[90],"events":[92],"detectable":[93],"them,":[95],"discusses":[97],"an":[98,109],"collecting,":[101],"storing,":[102],"analyzing":[104],"gathered":[107],"during":[108],"application":[110],"execution.":[111]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-02-09T09:26:11.010843","created_date":"2025-10-10T00:00:00"}
