{"id":"https://openalex.org/W2211652071","doi":"https://doi.org/10.1109/tvlsi.2013.2275071","title":"Improved Analytical Delay Models for RC-Coupled Interconnects","display_name":"Improved Analytical Delay Models for RC-Coupled Interconnects","publication_year":2013,"publication_date":"2013-08-22","ids":{"openalex":"https://openalex.org/W2211652071","doi":"https://doi.org/10.1109/tvlsi.2013.2275071","mag":"2211652071"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2013.2275071","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2275071","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024400429","display_name":"Feng Shi","orcid":"https://orcid.org/0000-0001-8870-5408"},"institutions":[{"id":"https://openalex.org/I186143895","display_name":"Lehigh University","ror":"https://ror.org/012afjb06","country_code":"US","type":"education","lineage":["https://openalex.org/I186143895"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Feng Shi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Lehigh University, Bethlehem, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Lehigh University, Bethlehem, PA, USA","institution_ids":["https://openalex.org/I186143895"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013653082","display_name":"Xuebin Wu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xuebin Wu","raw_affiliation_strings":["LSI Corporation, Milpitas, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LSI Corporation, Milpitas, CA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101582861","display_name":"Zhiyuan Yan","orcid":"https://orcid.org/0000-0003-2286-2771"},"institutions":[{"id":"https://openalex.org/I186143895","display_name":"Lehigh University","ror":"https://ror.org/012afjb06","country_code":"US","type":"education","lineage":["https://openalex.org/I186143895"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhiyuan Yan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Lehigh University, Bethlehem, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Lehigh University, Bethlehem, PA, USA","institution_ids":["https://openalex.org/I186143895"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6163,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.75200896,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"22","issue":"7","first_page":"1639","last_page":"1644"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.793813169002533},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.6369985938072205},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6298815608024597},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6007001996040344},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.46306103467941284},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.4594195485115051},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4499843120574951},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4430758059024811},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.42758065462112427},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2090958058834076},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.2044132649898529},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.14667075872421265}],"concepts":[{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.793813169002533},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.6369985938072205},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6298815608024597},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6007001996040344},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.46306103467941284},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.4594195485115051},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4499843120574951},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4430758059024811},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.42758065462112427},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2090958058834076},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.2044132649898529},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.14667075872421265},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2013.2275071","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2275071","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.769.1040","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.769.1040","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://arxiv.org/pdf/1304.0835.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1523576321","https://openalex.org/W1597473180","https://openalex.org/W1989297956","https://openalex.org/W2066910438","https://openalex.org/W2107415207","https://openalex.org/W2108368155","https://openalex.org/W2108543670","https://openalex.org/W2110477661","https://openalex.org/W2119039311","https://openalex.org/W2122401630","https://openalex.org/W2123692429","https://openalex.org/W2144406075","https://openalex.org/W2153558271","https://openalex.org/W2165208933","https://openalex.org/W2211652071","https://openalex.org/W4247998816","https://openalex.org/W4249751941","https://openalex.org/W4252202715","https://openalex.org/W6676462731","https://openalex.org/W6678425368"],"related_works":["https://openalex.org/W2114232017","https://openalex.org/W1927636319","https://openalex.org/W3015599398","https://openalex.org/W2188730438","https://openalex.org/W2792778858","https://openalex.org/W2367816239","https://openalex.org/W1875529755","https://openalex.org/W1997308464","https://openalex.org/W2123314372","https://openalex.org/W2114992783"],"abstract_inverted_index":{"As":[0],"process":[1],"technologies":[2],"scale":[3],"into":[4],"deep":[5],"submicrometer":[6],"region,":[7],"crosstalk":[8,67,72],"delay":[9,25,34,78,104],"is":[10],"becoming":[11],"increasingly":[12],"severe,":[13],"especially":[14],"for":[15,95,106],"global":[16],"on-chip":[17],"buses.":[18],"To":[19],"cope":[20],"with":[21],"this":[22,99],"problem,":[23],"accurate":[24],"models":[26,35,105],"of":[27,59],"coupled":[28,60,107],"interconnects":[29,61,108],"are":[30,40,44],"needed.":[31],"In":[32,98],"particular,":[33],"based":[36],"on":[37],"analytical":[38,77,103],"approaches":[39],"desirable,":[41],"because":[42],"they":[43],"not":[45,93],"only":[46],"largely":[47],"transparent":[48],"to":[49],"technology,":[50],"but":[51],"also":[52],"explicitly":[53],"establish":[54],"the":[55,82],"connections":[56],"between":[57],"delays":[58],"and":[62,91],"transition":[63],"patterns,":[64],"thereby":[65],"enabling":[66],"alleviating":[68],"techniques":[69],"such":[70,80],"as":[71,81],"avoidance":[73],"codes.":[74],"Unfortunately,":[75],"existing":[76],"models,":[79],"widely":[83],"cited":[84],"model":[85],"in":[86],"[1],":[87],"have":[88],"limited":[89],"accuracy":[90],"do":[92],"account":[94],"loading":[96],"capacitance.":[97],"brief,":[100],"we":[101],"propose":[102],"that":[109],"address":[110],"these":[111],"disadvantages.":[112]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-23T08:03:31.855105","created_date":"2025-10-10T00:00:00"}