{"id":"https://openalex.org/W2064465644","doi":"https://doi.org/10.1109/tvlsi.2013.2271054","title":"Simplifying Clock Gating Logic by Matching Factored Forms","display_name":"Simplifying Clock Gating Logic by Matching Factored Forms","publication_year":2013,"publication_date":"2013-07-16","ids":{"openalex":"https://openalex.org/W2064465644","doi":"https://doi.org/10.1109/tvlsi.2013.2271054","mag":"2064465644"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2013.2271054","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2271054","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031562748","display_name":"Inhak Han","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Inhak Han","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","Department of Electrical Engineering, Korea Advanced Institute of Science and Technology Daejeon Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology Daejeon Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","Department of Electrical Engineering, Korea Advanced Institute of Science and Technology Daejeon Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology Daejeon Korea","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157485424"],"apc_list":null,"apc_paid":null,"fwci":0.7046,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.74958513,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"22","issue":"6","first_page":"1338","last_page":"1349"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.8504488468170166},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.721432089805603},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6735278964042664},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5996438264846802},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.5690382719039917},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.5445799827575684},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.514549195766449},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.49630552530288696},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4712021052837372},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.4513890743255615},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43051230907440186},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.4167669713497162},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4040510952472687},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.38206106424331665},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.18120700120925903},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.12268486618995667},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10614562034606934},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09160348773002625},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.0900055468082428},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.0724618136882782}],"concepts":[{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.8504488468170166},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.721432089805603},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6735278964042664},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5996438264846802},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.5690382719039917},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.5445799827575684},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.514549195766449},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.49630552530288696},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4712021052837372},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.4513890743255615},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43051230907440186},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.4167669713497162},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4040510952472687},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.38206106424331665},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.18120700120925903},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.12268486618995667},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10614562034606934},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09160348773002625},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.0900055468082428},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.0724618136882782},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2013.2271054","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2271054","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1655990431","https://openalex.org/W1917288656","https://openalex.org/W1969440359","https://openalex.org/W1996445094","https://openalex.org/W2035342163","https://openalex.org/W2036887642","https://openalex.org/W2046948317","https://openalex.org/W2070298863","https://openalex.org/W2080267935","https://openalex.org/W2096050740","https://openalex.org/W2098560306","https://openalex.org/W2099251677","https://openalex.org/W2103122593","https://openalex.org/W2107895817","https://openalex.org/W2112476556","https://openalex.org/W2117880765","https://openalex.org/W2125121514","https://openalex.org/W2136047350","https://openalex.org/W2137564865","https://openalex.org/W2141047538","https://openalex.org/W2484538995","https://openalex.org/W2520093650","https://openalex.org/W3139969152","https://openalex.org/W3152276953","https://openalex.org/W4232340452","https://openalex.org/W4236218105"],"related_works":["https://openalex.org/W2805856399","https://openalex.org/W1936629927","https://openalex.org/W1939541994","https://openalex.org/W1621928919","https://openalex.org/W2114347552","https://openalex.org/W3140764919","https://openalex.org/W2064465644","https://openalex.org/W3140893992","https://openalex.org/W1593730165","https://openalex.org/W4235006579"],"abstract_inverted_index":{"Gate-level":[0],"clock":[1],"gating":[2,11,20,29,52,88,128],"starts":[3],"with":[4,7,63],"a":[5,28,136],"netlist,":[6],"partial":[8],"or":[9],"no":[10],"applied;":[12],"some":[13],"flip-flops":[14],"are":[15,57,79,91,99,112,119],"then":[16,37,80],"selected":[17],"for":[18,84,140],"further":[19],"to":[21,43,122],"reduce":[22],"the":[23,32,67,75,85,103,115],"circuit's":[24],"power":[25],"consumption,":[26],"and":[27,106,117],"logic":[30,116,129],"of":[31,66,70,87,133,149],"smallest":[33],"possible":[34],"size":[35],"must":[36],"be":[38],"synthesized.":[39],"We":[40],"show":[41],"how":[42],"do":[44],"this":[45],"by":[46,130],"factored":[47,55,64,104],"form":[48,125],"matching,":[49],"in":[50,54,74,102,114],"which":[51,141],"functions":[53,69,89],"forms":[56,65],"matched,":[58],"as":[59,61],"far":[60],"possible,":[62],"Boolean":[68,142],"existing":[71],"combinational":[72],"nodes":[73],"circuit;":[76],"additional":[77],"gates":[78],"introduced,":[81],"but":[82],"only":[83,144],"portion":[86],"that":[90,98,111],"not":[92],"matched.":[93],"Strong":[94],"matching":[95,108,126],"identifies":[96],"matches":[97,110],"explicitly":[100],"present":[101],"forms,":[105],"weak":[107],"seeks":[109],"implicit":[113],"thus":[118],"more":[120],"difficult":[121],"discover.":[123],"Factored":[124],"reduces":[127],"an":[131,146],"average":[132,147],"24%,":[134],"over":[135],"few":[137],"test":[138],"circuits,":[139],"division":[143],"achieves":[145],"reduction":[148],"8%.":[150]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}