{"id":"https://openalex.org/W2036753474","doi":"https://doi.org/10.1109/tvlsi.2013.2270362","title":"14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability","display_name":"14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability","publication_year":2013,"publication_date":"2013-10-07","ids":{"openalex":"https://openalex.org/W2036753474","doi":"https://doi.org/10.1109/tvlsi.2013.2270362","mag":"2036753474"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2013.2270362","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2270362","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108047268","display_name":"Hao-Chiao Hong","orcid":"https://orcid.org/0000-0003-0757-1001"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Hao-Chiao Hong","raw_affiliation_strings":["Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060228101","display_name":"Yung-Shun Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Shun Chen","raw_affiliation_strings":["Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","Institute of Electrical Control Engineering National Chiao Tung University Hsinchu Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Institute of Electrical Control Engineering National Chiao Tung University Hsinchu Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048730663","display_name":"Wei-Chieh Fang","orcid":"https://orcid.org/0000-0002-5106-4878"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Chieh Fang","raw_affiliation_strings":["Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","Institute of Electrical Control Engineering National Chiao Tung University Hsinchu Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Institute of Electrical Control Engineering National Chiao Tung University Hsinchu Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5108047268"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.58674572,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.69520507,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"22","issue":"6","first_page":"1238","last_page":"1247"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6289855241775513},{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.6119632124900818},{"id":"https://openalex.org/keywords/effective-number-of-bits","display_name":"Effective number of bits","score":0.5657778978347778},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5626144409179688},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.522961437702179},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.5209561586380005},{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.5137932896614075},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5051410794258118},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.4742269217967987},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.4712531864643097},{"id":"https://openalex.org/keywords/analog-to-digital-converter","display_name":"Analog-to-digital converter","score":0.4324713349342346},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.42151182889938354},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36825239658355713},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3629930317401886},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3029458224773407},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.25154033303260803},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20528778433799744}],"concepts":[{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6289855241775513},{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.6119632124900818},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.5657778978347778},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5626144409179688},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.522961437702179},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.5209561586380005},{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.5137932896614075},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5051410794258118},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.4742269217967987},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.4712531864643097},{"id":"https://openalex.org/C2777271169","wikidata":"https://www.wikidata.org/wiki/Q190169","display_name":"Analog-to-digital converter","level":3,"score":0.4324713349342346},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.42151182889938354},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36825239658355713},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3629930317401886},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3029458224773407},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.25154033303260803},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20528778433799744},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2013.2270362","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2270362","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5960170967","display_name":null,"funder_award_id":"NSC101-2221-E009-166","funder_id":"https://openalex.org/F4320321040","funder_display_name":"National Science Council"}],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1536945048","https://openalex.org/W1586613304","https://openalex.org/W1737812324","https://openalex.org/W1970258631","https://openalex.org/W1972932950","https://openalex.org/W1979798093","https://openalex.org/W1986483493","https://openalex.org/W1998656565","https://openalex.org/W2011170126","https://openalex.org/W2030822983","https://openalex.org/W2033829613","https://openalex.org/W2081870816","https://openalex.org/W2120200547","https://openalex.org/W2125666370","https://openalex.org/W2133992557","https://openalex.org/W2143310750","https://openalex.org/W2145458182","https://openalex.org/W2155544283","https://openalex.org/W2164893802","https://openalex.org/W3150891300","https://openalex.org/W4252370165","https://openalex.org/W4256013926","https://openalex.org/W4256065124","https://openalex.org/W6649811590","https://openalex.org/W6670889262"],"related_works":["https://openalex.org/W2054489929","https://openalex.org/W2021405064","https://openalex.org/W1496095114","https://openalex.org/W2759515872","https://openalex.org/W3082766528","https://openalex.org/W2744643448","https://openalex.org/W2765332907","https://openalex.org/W4376139100","https://openalex.org/W2024969921","https://openalex.org/W2341231357"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,45,49,54,72,75,78,81,85,91,95,106,112,119,123,126,132,146,157,161,175,181,187,190,205],"design":[4,86,124],"and":[5,37,84,114,148,208,218,236,241,248,255],"test":[6,139,143,172],"of":[7,30,74,117,163,184,189,193],"a":[8,31,38,164,212,219,225,245],"14":[9,232],"GSps,":[10],"four-bit":[11],"data":[12,26],"converter":[13,27,35,42,46],"pair":[14,28,210],"in":[15,77],"90":[16],"nm":[17],"CMOS":[18],"suitable":[19],"for":[20],"implementing":[21],"advanced":[22],"serial":[23],"links.":[24],"The":[25,141,170,200,234],"consists":[29],"noninterleaved":[32,39],"flash":[33],"analog-to-digital":[34],"(ADC)":[36],"current-steering":[40],"digital-to-analog":[41],"(DAC).":[43],"Both":[44],"designs":[47],"adopt":[48],"wave-pipelining":[50],"technique":[51],"to":[52,70,94,104,135],"increase":[53],"available":[55],"signal":[56],"settling":[57],"time.":[58],"Through":[59],"detailed":[60],"analysis,":[61],"we":[62,89],"show":[63,203],"that":[64,151,204],"cascading":[65],"three":[66],"active":[67],"feedback":[68,197],"preamplifiers":[69],"implement":[71],"cores":[73],"comparators":[76],"ADC":[79,147,185,207,235],"balances":[80],"power":[82,107],"budget":[83],"difficulty":[87,113],"when":[88],"push":[90],"sampling":[92],"rate":[93],"process":[96],"limit.":[97],"Current":[98],"mode":[99,144,173],"logic":[100,168],"gates":[101],"are":[102],"used":[103],"alleviate":[105],"bouncing":[108],"issue.":[109],"To":[110],"address":[111],"high":[115,166],"cost":[116],"testing":[118],"extremely":[120],"high-speed":[121],"converters,":[122],"embeds":[125],"simple":[127],"design-for-testability":[128],"circuits":[129],"cooperating":[130],"with":[131,224],"on-chip":[133],"resources":[134],"provide":[136],"two":[137],"cost-effective":[138],"modes.":[140],"first":[142],"cascades":[145],"DAC":[149,191,209,237],"so":[150],"they":[152],"can":[153],"be":[154],"tested":[155],"at":[156,231],"rated":[158],"speed":[159,167],"without":[160],"need":[162],"very":[165],"analyzer.":[169],"second":[171],"enables":[174],"eye":[176],"diagram":[177],"tests":[178],"by":[179],"shuffling":[180],"digital":[182],"outputs":[183],"as":[186],"inputs":[188],"instead":[192],"adopting":[194],"conventional":[195],"linear":[196],"shift":[198],"register.":[199],"experimental":[201],"results":[202],"cascaded":[206],"achieves":[211],"31.0":[213],"dBc":[214],"spurious-free":[215],"dynamic":[216],"range":[217],"25.9":[220],"dB":[221],"signal-to-noise-and-distortion":[222],"ratio":[223],"1.11":[226],"GHz,":[227],"-1":[228],"dBFS":[229],"stimulus":[230],"GSps.":[233],"consume":[238],"214":[239],"mW":[240,243],"85":[242],"from":[244],"1.0-V":[246],"supply":[247],"occupy":[249],"0.1575":[250],"mm":[251,257],"<sup":[252,258],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[253,259],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[254,260],"0.0636":[256],",":[261],"respectively.":[262]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
