{"id":"https://openalex.org/W2074919416","doi":"https://doi.org/10.1109/tvlsi.2013.2266281","title":"Layout-Based Refined NPSF Model for DRAM Characterization and Testing","display_name":"Layout-Based Refined NPSF Model for DRAM Characterization and Testing","publication_year":2013,"publication_date":"2013-06-25","ids":{"openalex":"https://openalex.org/W2074919416","doi":"https://doi.org/10.1109/tvlsi.2013.2266281","mag":"2074919416"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2013.2266281","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2266281","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025952927","display_name":"Yiorgos Sfikas","orcid":null},"institutions":[{"id":"https://openalex.org/I194019607","display_name":"University of Ioannina","ror":"https://ror.org/01qg3j183","country_code":"GR","type":"education","lineage":["https://openalex.org/I194019607"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Yiorgos Sfikas","raw_affiliation_strings":["Department of Computer Science, University of Ioannina, Ioannina, Greece","Dept. of Computer Science, Univ. of Ioannina, Ioannina, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Ioannina, Ioannina, Greece","institution_ids":["https://openalex.org/I194019607"]},{"raw_affiliation_string":"Dept. of Computer Science, Univ. of Ioannina, Ioannina, Greece","institution_ids":["https://openalex.org/I194019607"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036684985","display_name":"Yiorgos Tsiatouhas","orcid":"https://orcid.org/0000-0001-8408-6929"},"institutions":[{"id":"https://openalex.org/I194019607","display_name":"University of Ioannina","ror":"https://ror.org/01qg3j183","country_code":"GR","type":"education","lineage":["https://openalex.org/I194019607"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Yiorgos E. Tsiatouhas","raw_affiliation_strings":["Department of Computer Science, University of Ioannina, Ioannina, Greece","Dept. of Computer Science, Univ. of Ioannina, Ioannina, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Ioannina, Ioannina, Greece","institution_ids":["https://openalex.org/I194019607"]},{"raw_affiliation_string":"Dept. of Computer Science, Univ. of Ioannina, Ioannina, Greece","institution_ids":["https://openalex.org/I194019607"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005739146","display_name":"Said Hamdioui","orcid":"https://orcid.org/0000-0002-8961-0387"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Said Hamdioui","raw_affiliation_strings":["Computer Engineering Laboratory, Delft University of Technology, Delft, CD, The Netherlands","[Computer Engineering Laboratory Delft University of Technology, Delft, CD, The Netherlands]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Laboratory, Delft University of Technology, Delft, CD, The Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"[Computer Engineering Laboratory Delft University of Technology, Delft, CD, The Netherlands]","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6343,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.70978298,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"22","issue":"6","first_page":"1446","last_page":"1450"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9544335007667542},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.607812762260437},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.5406375527381897},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4872542917728424},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4395824074745178},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.4211537539958954},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40264856815338135},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3668327331542969},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36305344104766846},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34288325905799866},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2655366361141205},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2394474446773529},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.11849001049995422},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.08119100332260132},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08037474751472473}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9544335007667542},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.607812762260437},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.5406375527381897},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4872542917728424},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4395824074745178},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.4211537539958954},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40264856815338135},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3668327331542969},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36305344104766846},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34288325905799866},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2655366361141205},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2394474446773529},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.11849001049995422},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.08119100332260132},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08037474751472473},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2013.2266281","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2266281","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.6700000166893005}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W289624287","https://openalex.org/W617647215","https://openalex.org/W653285986","https://openalex.org/W1503360612","https://openalex.org/W1511224872","https://openalex.org/W1536696925","https://openalex.org/W1922417446","https://openalex.org/W1979920181","https://openalex.org/W2015684960","https://openalex.org/W2023834387","https://openalex.org/W2045354801","https://openalex.org/W2059288509","https://openalex.org/W2106060433","https://openalex.org/W2118365271","https://openalex.org/W2120523301","https://openalex.org/W2129393873","https://openalex.org/W2138169794","https://openalex.org/W2139728303","https://openalex.org/W2145197558","https://openalex.org/W2145603583","https://openalex.org/W2156748177","https://openalex.org/W2183309359","https://openalex.org/W6629987606","https://openalex.org/W6640155157","https://openalex.org/W6680501067","https://openalex.org/W6681419126","https://openalex.org/W6686149710"],"related_works":["https://openalex.org/W2518930778","https://openalex.org/W2979599569","https://openalex.org/W3007039213","https://openalex.org/W2533585248","https://openalex.org/W2559795407","https://openalex.org/W2944414554","https://openalex.org/W2000563648","https://openalex.org/W3130092517","https://openalex.org/W3015923041","https://openalex.org/W2582197177"],"abstract_inverted_index":{"As":[0,89],"dynamic":[1],"random":[2],"access":[3],"memories":[4],"(DRAMs)":[5],"are":[6,18,56],"becoming":[7],"denser":[8],"with":[9,109,134],"technology":[10],"scaling,":[11],"more":[12,117],"complex":[13],"fault":[14,30],"behaviors":[15,39],"emerge;":[16],"examples":[17],"leakage,":[19],"coupling":[20,131],"effects,":[21,132],"and":[22,40,59,77,83,129,153],"cell":[23],"neighborhoods":[24],"interaction.":[25],"The":[26],"neighborhood":[27],"pattern":[28],"sensitive":[29],"(NPSF)":[31],"model":[32,82],"is":[33,97,106,116],"suitable":[34,155],"to":[35,75],"address":[36],"such":[37],"faulty":[38],"identify":[41],"them":[42],"during":[43],"the":[44,80,85,93,103,136,145,157,163],"characterization":[45],"and/or":[46],"test":[47,54,86,113,137],"of":[48,159],"new":[49],"DRAM":[50,95],"chips.":[51],"However,":[52],"NPSF":[53,81,101,149],"algorithms":[55],"extremely":[57],"time-consuming":[58],"therefore":[60],"not":[61],"economically":[62,151],"affordable.":[63],"In":[64],"this":[65],"brief,":[66],"we":[67],"show":[68],"how":[69],"layout":[70],"information":[71],"can":[72],"be":[73],"used":[74],"refine":[76],"significantly":[78],"simplify":[79],"reduce":[84],"time":[87,111,139],"complexity.":[88],"a":[90,110],"case":[91],"study,":[92],"folded":[94],"array":[96],"considered.":[98],"A":[99],"realistic":[100],"model,":[102],"\u0394-type":[104],"neighborhood,":[105],"introduced":[107],"together":[108],"efficient":[112],"algorithm":[114,138],"which":[115],"than":[118,121],"two-times":[119],"cheaper":[120],"traditional":[122],"ones.":[123],"Even":[124],"when":[125],"incorporating":[126],"bit-line":[127],"influence":[128],"word-line":[130],"along":[133],"NPSFs,":[135],"complexity":[140],"almost":[141],"remains":[142],"unaltered.":[143],"Therefore,":[144],"proposed":[146],"approach":[147],"makes":[148],"testing":[150],"affordable,":[152],"hence,":[154],"for":[156],"characterization/test":[158],"dense":[160],"DRAMs":[161],"in":[162],"nanoera.":[164]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}