{"id":"https://openalex.org/W1965738274","doi":"https://doi.org/10.1109/tvlsi.2013.2265662","title":"Variation-Aware Variable Latency Design","display_name":"Variation-Aware Variable Latency Design","publication_year":2013,"publication_date":"2013-07-16","ids":{"openalex":"https://openalex.org/W1965738274","doi":"https://doi.org/10.1109/tvlsi.2013.2265662","mag":"1965738274"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2013.2265662","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2265662","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043629600","display_name":"Saket Gupta","orcid":"https://orcid.org/0000-0003-4541-5798"},"institutions":[{"id":"https://openalex.org/I1296127346","display_name":"Broadcom (Israel)","ror":"https://ror.org/01jsrac29","country_code":"IL","type":"company","lineage":["https://openalex.org/I1296127346","https://openalex.org/I4210127325"]},{"id":"https://openalex.org/I4210127325","display_name":"Broadcom (United States)","ror":"https://ror.org/035gt5s03","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127325"]}],"countries":["IL","US"],"is_corresponding":false,"raw_author_name":"Saket Gupta","raw_affiliation_strings":["Library Development, Broadcom Corporation, Edina, MN, USA","Libr. Dev., Broadcom Corp., Edina, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Library Development, Broadcom Corporation, Edina, MN, USA","institution_ids":["https://openalex.org/I4210127325"]},{"raw_affiliation_string":"Libr. Dev., Broadcom Corp., Edina, MN, USA","institution_ids":["https://openalex.org/I1296127346"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068714995","display_name":"Sachin S. Sapatnekar","orcid":"https://orcid.org/0000-0002-5353-2364"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sachin S. Sapatnekar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","Dept. of Electr. & Comput. Eng, Univ. of Minnesota, Minneapolis, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Univ. of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7201,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.73362178,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"22","issue":"5","first_page":"1106","last_page":"1117"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6763138771057129},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6040310859680176},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5653214454650879},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5649610161781311},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4774516224861145},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4670350253582001},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.45130786299705505},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4429023861885071},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4413856565952301},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.43939658999443054},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4387591481208801},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4386466443538666},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4118831753730774},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.3025892972946167},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.28019171953201294},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.25675374269485474},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1824909746646881},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.13990461826324463},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09520509839057922},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08414578437805176},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0814143717288971}],"concepts":[{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6763138771057129},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6040310859680176},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5653214454650879},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5649610161781311},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4774516224861145},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4670350253582001},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.45130786299705505},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4429023861885071},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4413856565952301},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.43939658999443054},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4387591481208801},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4386466443538666},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4118831753730774},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3025892972946167},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28019171953201294},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.25675374269485474},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1824909746646881},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.13990461826324463},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09520509839057922},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08414578437805176},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0814143717288971},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2013.2265662","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2265662","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.432.6401","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.432.6401","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.umn.edu/users/sachin/jnl/tvlsi14sg.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1973248777","https://openalex.org/W2038840127","https://openalex.org/W2051865944","https://openalex.org/W2095665333","https://openalex.org/W2110722301","https://openalex.org/W2112709910","https://openalex.org/W2127036509","https://openalex.org/W2136103183","https://openalex.org/W2136328167","https://openalex.org/W2150959181","https://openalex.org/W2151802820","https://openalex.org/W2154018883","https://openalex.org/W2154168135","https://openalex.org/W2155829479","https://openalex.org/W2163997673","https://openalex.org/W2178304595","https://openalex.org/W4236140030","https://openalex.org/W6643513670"],"related_works":["https://openalex.org/W2550704533","https://openalex.org/W2827496155","https://openalex.org/W1973774436","https://openalex.org/W2890026549","https://openalex.org/W3092420867","https://openalex.org/W2115729972","https://openalex.org/W2793417036","https://openalex.org/W2042032654","https://openalex.org/W2158291854","https://openalex.org/W2123535323"],"abstract_inverted_index":{"Although":[0],"typical":[1],"digital":[2],"circuits":[3],"are":[4,155],"designed":[5],"so":[6],"that":[7,85,105],"the":[8,17,58,70,101,133,139],"clock":[9,28,41,48],"period":[10],"satisfies":[11],"worst":[12],"case":[13],"path":[14,98,110,128,149],"delay":[15],"constraints,":[16],"average":[18],"input":[19],"excitation":[20],"often":[21],"completes":[22],"computation":[23],"in":[24,118,153],"less":[25],"than":[26],"a":[27,77,109,119,145,158],"cycle.":[29],"Variable":[30],"latency":[31],"units":[32],"(VLUs)":[33],"allow":[34],"for":[35,43,50,81,144],"improved":[36],"throughput":[37,66,154,169],"by":[38,96],"allowing":[39],"one":[40],"cycle":[42],"some":[44],"computations,":[45],"and":[46,136],"two":[47,59],"cycles":[49],"others,":[51],"using":[52],"hold":[53,141],"logic":[54],"to":[55,69,114,125],"differentiate":[56],"between":[57],"cases.":[60],"However,":[61],"they":[62],"may":[63],"experience":[64],"significant":[65,151],"losses":[67],"due":[68],"effects":[71],"of":[72,108,148,160],"process":[73],"variations.":[74],"We":[75,93,122],"develop":[76],"combined":[78],"presilicon-postsilicon":[79],"technique":[80],"variation-aware":[82],"VLU":[83],"design":[84],"ensures":[86],"high":[87],"throughputs":[88],"across":[89],"all":[90],"manufactured":[91,120],"chips.":[92],"achieve":[94],"this":[95],"identifying":[97],"clusters":[99,129],"at":[100,132],"presilicon":[102],"stage,":[103],"such":[104],"each":[106],"element":[107],"cluster":[111],"is":[112,130],"likely":[113],"be":[115],"similarly":[116],"critical":[117,131],"part.":[121],"use":[123],"sensors":[124],"determine":[126],"which":[127],"postsilicon":[134],"stage":[135],"then":[137],"activate":[138],"appropriate":[140],"logics.":[142],"Practically,":[143],"small":[146],"number":[147],"clusters,":[150],"improvements":[152],"achievable.":[156],"On":[157],"set":[159],"32-nm":[161],"PTM-based":[162],"ISCAS89":[163],"circuits,":[164],"our":[165],"scheme":[166],"offers":[167],"15.1%":[168],"enhancements":[170],"with":[171],"only":[172],"3.3%":[173],"area":[174],"overhead.":[175]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
