{"id":"https://openalex.org/W2167065655","doi":"https://doi.org/10.1109/tvlsi.2013.2257902","title":"Logical Effort for CMOS-Based Dual Mode Logic Gates","display_name":"Logical Effort for CMOS-Based Dual Mode Logic Gates","publication_year":2014,"publication_date":"2014-04-22","ids":{"openalex":"https://openalex.org/W2167065655","doi":"https://doi.org/10.1109/tvlsi.2013.2257902","mag":"2167065655"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2013.2257902","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2257902","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032341525","display_name":"Itamar Levi","orcid":"https://orcid.org/0000-0002-5591-5799"},"institutions":[{"id":"https://openalex.org/I124227911","display_name":"Ben-Gurion University of the Negev","ror":"https://ror.org/05tkyf982","country_code":"IL","type":"education","lineage":["https://openalex.org/I124227911"]},{"id":"https://openalex.org/I4210089528","display_name":"The Technological College of Beer Sheva","ror":"https://ror.org/00bzfhs56","country_code":"IL","type":"education","lineage":["https://openalex.org/I4210089528"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Itamar Levi","raw_affiliation_strings":["Department of Electrical and computer Engineering, Beer-Sheva, Israel","Dept. of Electr. & Comput. Eng., Ben-Gurion Univ., Beer Sheva, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and computer Engineering, Beer-Sheva, Israel","institution_ids":["https://openalex.org/I4210089528"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Ben-Gurion Univ., Beer Sheva, Israel","institution_ids":["https://openalex.org/I124227911"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110228786","display_name":"Alexander Belenky","orcid":null},"institutions":[{"id":"https://openalex.org/I124227911","display_name":"Ben-Gurion University of the Negev","ror":"https://ror.org/05tkyf982","country_code":"IL","type":"education","lineage":["https://openalex.org/I124227911"]},{"id":"https://openalex.org/I4210089528","display_name":"The Technological College of Beer Sheva","ror":"https://ror.org/00bzfhs56","country_code":"IL","type":"education","lineage":["https://openalex.org/I4210089528"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Alexander Belenky","raw_affiliation_strings":["Department of Electrical and computer Engineering, Beer-Sheva, Israel","Dept. of Electr. & Comput. Eng., Ben-Gurion Univ., Beer Sheva, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and computer Engineering, Beer-Sheva, Israel","institution_ids":["https://openalex.org/I4210089528"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Ben-Gurion Univ., Beer Sheva, Israel","institution_ids":["https://openalex.org/I124227911"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065902823","display_name":"Alexander Fish","orcid":"https://orcid.org/0000-0002-4994-1536"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]},{"id":"https://openalex.org/I4210160816","display_name":"Alzheimer's Association of Israel","ror":"https://ror.org/0561tpp86","country_code":"IL","type":"nonprofit","lineage":["https://openalex.org/I4210160816"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Alexander Fish","raw_affiliation_strings":["Faculty of Engineering, Ramat Gan, Israel","Fac. of Eng., Bar Ilan Univ., Ramat-Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Ramat Gan, Israel","institution_ids":["https://openalex.org/I4210160816"]},{"raw_affiliation_string":"Fac. of Eng., Bar Ilan Univ., Ramat-Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8647,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.87745537,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"22","issue":"5","first_page":"1042","last_page":"1053"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.622505247592926},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6028134822845459},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5976278185844421},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5752224326133728},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.5448955297470093},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5325120091438293},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.5222200155258179},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5142645239830017},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.5005793571472168},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4940953552722931},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45930349826812744},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.35206690430641174},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.3412008285522461},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.274539589881897},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15380433201789856},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10115912556648254}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.622505247592926},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6028134822845459},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5976278185844421},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5752224326133728},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.5448955297470093},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5325120091438293},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5222200155258179},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5142645239830017},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.5005793571472168},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4940953552722931},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45930349826812744},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.35206690430641174},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.3412008285522461},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.274539589881897},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15380433201789856},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10115912556648254}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2013.2257902","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2013.2257902","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1479741658","https://openalex.org/W1817545098","https://openalex.org/W2037299409","https://openalex.org/W2038049046","https://openalex.org/W2051302843","https://openalex.org/W2088115909","https://openalex.org/W2104596471","https://openalex.org/W2108971405","https://openalex.org/W2109288479","https://openalex.org/W2114187135","https://openalex.org/W2115404976","https://openalex.org/W2118396866","https://openalex.org/W2125778215","https://openalex.org/W2127656032","https://openalex.org/W2151092072","https://openalex.org/W2153090913","https://openalex.org/W2154930846","https://openalex.org/W2159868837","https://openalex.org/W2164509657","https://openalex.org/W2185508384","https://openalex.org/W3103339143","https://openalex.org/W4240274300","https://openalex.org/W6638491868","https://openalex.org/W6659431876","https://openalex.org/W6675891092","https://openalex.org/W6683868758"],"related_works":["https://openalex.org/W3015599398","https://openalex.org/W2529692069","https://openalex.org/W2791258803","https://openalex.org/W2150435684","https://openalex.org/W2132334743","https://openalex.org/W2769457990","https://openalex.org/W2901267638","https://openalex.org/W2082591327","https://openalex.org/W2260374957","https://openalex.org/W1902382435"],"abstract_inverted_index":{"Recently,":[0],"a":[1,156],"novel":[2],"dual":[3],"mode":[4,41,139],"logic":[5,11,62],"(DML)":[6],"family":[7,63],"was":[8],"proposed.":[9],"This":[10,100],"allows":[12,88,112],"operation":[13],"in":[14,38,45,155],"two":[15],"modes:":[16],"1)":[17],"static":[18,40,61],"and":[19,42,56,65,94,107,128,147],"2)":[20],"dynamic":[21,47,138],"modes.":[22],"DML":[23,51,83,98],"gates,":[24],"which":[25,111],"can":[26],"be":[27],"switched":[28],"between":[29],"these":[30],"modes":[31],"on-the-fly,":[32],"feature":[33],"very":[34,54],"low":[35],"power":[36],"dissipation":[37],"the":[39,46,75,81,137,150],"high":[43],"performance":[44],"mode.":[48],"A":[49],"basic":[50],"gate":[52,64],"is":[53,57,101,134,145,153],"simple":[55],"composed":[58],"of":[59,97,105,115,123,140,149],"any":[60],"an":[66],"additional":[67],"clocked":[68],"transistor.":[69],"In":[70],"this":[71],"paper,":[72],"we":[73],"introduce":[74],"logical":[76],"effort":[77],"(LE)":[78],"methodology":[79,87,152],"for":[80,136],"CMOS-based":[82],"family.":[84],"The":[85,131],"proposed":[86,132,151],"path":[89],"length":[90],"minimization,":[91],"delay":[92,95,129],"optimization,":[93],"estimation":[96],"logic.":[99],"done":[102],"by":[103],"development":[104],"complete":[106],"approximated":[108],"LE":[109],"models,":[110],"easy":[113],"extraction":[114],"design":[116],"optimization":[117,133],"parameters,":[118],"such":[119],"as":[120],"optimum":[121],"number":[122],"stages,":[124],"gates":[125],"sizing":[126],"factors,":[127],"estimations.":[130],"shown":[135,154],"operation.":[141],"Theoretical":[142],"mathematical":[143],"analysis":[144],"presented,":[146],"efficiency":[148],"standard":[157],"40-nm":[158],"CMOS":[159],"process.":[160]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}