{"id":"https://openalex.org/W2026812171","doi":"https://doi.org/10.1109/tvlsi.2012.2230035","title":"Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise","display_name":"Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise","publication_year":2013,"publication_date":"2013-01-11","ids":{"openalex":"https://openalex.org/W2026812171","doi":"https://doi.org/10.1109/tvlsi.2012.2230035","mag":"2026812171"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2012.2230035","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2230035","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/182127","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100385218","display_name":"Xu Hu","orcid":"https://orcid.org/0000-0002-4030-4899"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Hu Xu","raw_affiliation_strings":["Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","Integrated Systems Lab, EPFL,Lausanne,Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Integrated Systems Lab, EPFL,Lausanne,Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031542707","display_name":"Vasilis F. Pavlidis","orcid":"https://orcid.org/0000-0002-4063-4652"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Vasilis F. Pavlidis","raw_affiliation_strings":["School of Computer Science, University of Manchester, Manchester, UK","Sch. of Comput. Sci., Univ. of Manchester, Manchester, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Sch. of Comput. Sci., Univ. of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103004961","display_name":"Xifan Tang","orcid":"https://orcid.org/0000-0003-2203-3981"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Xifan Tang","raw_affiliation_strings":["Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","Integrated Systems Lab, EPFL,Lausanne,Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Integrated Systems Lab, EPFL,Lausanne,Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033415719","display_name":"Wayne Burleson","orcid":"https://orcid.org/0000-0002-7068-4351"},"institutions":[{"id":"https://openalex.org/I24603500","display_name":"University of Massachusetts Amherst","ror":"https://ror.org/0072zz521","country_code":"US","type":"education","lineage":["https://openalex.org/I24603500"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wayne Burleson","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, Amherst, MA, USA","Dept. of Electr. & Comput. Eng., Univ. of Massachusetts Amherst, Amherst, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, Amherst, MA, USA","institution_ids":["https://openalex.org/I24603500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Massachusetts Amherst, Amherst, MA, USA","institution_ids":["https://openalex.org/I24603500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","Integrated Systems Lab, EPFL,Lausanne,Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Integrated Systems Lab, EPFL,Lausanne,Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4092,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.83342916,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"21","issue":"12","first_page":"2226","last_page":"2239"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8185507655143738},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.7838019132614136},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6614173054695129},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.6222501993179321},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6051067113876343},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5373564958572388},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5342152714729309},{"id":"https://openalex.org/keywords/standard-deviation","display_name":"Standard deviation","score":0.4416269063949585},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4272104799747467},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.42172926664352417},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.41464629769325256},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.3185741901397705},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3022816777229309},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2932829260826111},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2525698244571686},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.24433183670043945},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.1528395414352417},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15150311589241028}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8185507655143738},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.7838019132614136},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6614173054695129},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.6222501993179321},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6051067113876343},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5373564958572388},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5342152714729309},{"id":"https://openalex.org/C22679943","wikidata":"https://www.wikidata.org/wiki/Q159375","display_name":"Standard deviation","level":2,"score":0.4416269063949585},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4272104799747467},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.42172926664352417},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.41464629769325256},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3185741901397705},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3022816777229309},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2932829260826111},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2525698244571686},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.24433183670043945},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.1528395414352417},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15150311589241028},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/tvlsi.2012.2230035","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2230035","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.720.3455","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.720.3455","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.man.ac.uk/%7Epavlidiv/pubs/TVLSI_13.pdf","raw_type":"text"},{"id":"pmh:oai:infoscience.epfl.ch:182127","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/182127","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/0247f5e4-c7df-4899-b00d-e8fb7a72bb58","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/0247f5e4-c7df-4899-b00d-e8fb7a72bb58","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Xu, H, Pavlidis, V F, Tang, X, Burleson, W & De Micheli, G 2013, 'Timing uncertainty in 3-D clock trees due to process variations and power supply noise', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 12, 6410052, pp. 2226-2239. https://doi.org/10.1109/TVLSI.2012.2230035","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:pure.atira.dk:publications/0247f5e4-c7df-4899-b00d-e8fb7a72bb58","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/timing-uncertainty-in-3d-clock-trees-due-to-process-variations-and-power-supply-noise(0247f5e4-c7df-4899-b00d-e8fb7a72bb58).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Xu, H, Pavlidis, V F, Tang, X, Burleson, W & De Micheli, G 2013, 'Timing uncertainty in 3-D clock trees due to process variations and power supply noise', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 12, 6410052, pp. 2226-2239. https://doi.org/10.1109/TVLSI.2012.2230035","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:182127","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/182127","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6399999856948853}],"awards":[{"id":"https://openalex.org/G2907617717","display_name":"Guaranteeing Signal and Power Integrity for Three-Dimensional (3-D)","funder_award_id":"126517","funder_id":"https://openalex.org/F4320320924","funder_display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320320924","display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","ror":"https://ror.org/00yjd3n13"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W89584938","https://openalex.org/W115185706","https://openalex.org/W599165874","https://openalex.org/W1693570377","https://openalex.org/W1982802100","https://openalex.org/W1990679103","https://openalex.org/W2007083443","https://openalex.org/W2046574526","https://openalex.org/W2062366285","https://openalex.org/W2096486545","https://openalex.org/W2098764315","https://openalex.org/W2106565868","https://openalex.org/W2108271947","https://openalex.org/W2109314689","https://openalex.org/W2110392223","https://openalex.org/W2114586573","https://openalex.org/W2116296320","https://openalex.org/W2116739712","https://openalex.org/W2122915341","https://openalex.org/W2125669810","https://openalex.org/W2129785295","https://openalex.org/W2133667515","https://openalex.org/W2136328167","https://openalex.org/W2138748603","https://openalex.org/W2148292324","https://openalex.org/W2154194029","https://openalex.org/W2155707315","https://openalex.org/W2158473722","https://openalex.org/W2158486845","https://openalex.org/W2159856958","https://openalex.org/W2164515066","https://openalex.org/W2169934076","https://openalex.org/W2481508967","https://openalex.org/W2485074729","https://openalex.org/W2629157711","https://openalex.org/W2788706082","https://openalex.org/W3146255990","https://openalex.org/W4238724481","https://openalex.org/W4301349926"],"related_works":["https://openalex.org/W2144282137","https://openalex.org/W2154194029","https://openalex.org/W2127379989","https://openalex.org/W2028052815","https://openalex.org/W2066822161","https://openalex.org/W2391115906","https://openalex.org/W3201048403","https://openalex.org/W2169934076","https://openalex.org/W2112814021","https://openalex.org/W1999924508"],"abstract_inverted_index":{"Clock":[0],"distribution":[1],"networks":[2],"are":[3,77,98,106,158],"affected":[4],"by":[5,148],"different":[6,133],"sources":[7],"of":[8,18,28,32,45,59,84,90,120,137,156],"variations.":[9],"The":[10,43,57,115,140],"resulting":[11],"clock":[12,33,39,149],"uncertainty":[13],"significantly":[14],"affects":[15],"the":[16,49,82,110,132,145,178],"frequency":[17],"a":[19,25,175],"circuit.":[20],"To":[21],"support":[22],"this":[23,85],"analysis,":[24],"statistical":[26],"model":[27],"skitter,":[29],"which":[30,80],"consists":[31],"skew":[34],"and":[35,51,72,117,127,135,144],"jitter,":[36],"for":[37],"3-D":[38,94,100,164],"trees":[40,150],"is":[41,55,61,151],"introduced.":[42],"effect":[44],"skitter":[46,60,111,121,143,162,180],"on":[47],"both":[48],"setup":[50],"hold":[52],"time":[53],"slacks":[54],"modeled.":[56],"variation":[58],"shown":[62],"to":[63,67,108,125,131,160,170,182],"be":[64],"underestimated":[65],"up":[66,124,181],"36%":[68],"if":[69],"process":[70],"variations":[71],"dynamic":[73],"power":[74,146],"supply":[75,91,138],"noise":[76,92],"considered":[78],"separately,":[79],"highlights":[81],"importance":[83],"unified":[86],"treatment.":[87],"Potential":[88],"scenarios":[89],"in":[93,163,177],"integrated":[95],"circuits":[96,101],"(ICs)":[97],"investigated.":[99],"generated":[102],"from":[103],"industrial":[104,171],"benchmarks":[105],"simulated":[107],"show":[109,174],"under":[112],"these":[113,168],"scenarios.":[114],"mean":[116,179],"standard":[118],"deviation":[119],"can":[122],"vary":[123],"60%":[126],"51%,":[128],"respectively,":[129],"due":[130],"amplitudes":[134],"phases":[136],"noise.":[139],"tradeoff":[141],"between":[142],"consumed":[147],"also":[152],"shown.":[153],"A":[154],"set":[155],"guidelines":[157,169],"presented":[159],"decrease":[161,176],"ICs.":[165],"By":[166],"applying":[167],"benchmarks,":[172],"simulations":[173],"31%.":[183]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}