{"id":"https://openalex.org/W1971325875","doi":"https://doi.org/10.1109/tvlsi.2012.2220387","title":"1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback Technique","display_name":"1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback Technique","publication_year":2012,"publication_date":"2012-11-21","ids":{"openalex":"https://openalex.org/W1971325875","doi":"https://doi.org/10.1109/tvlsi.2012.2220387","mag":"1971325875"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2012.2220387","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2220387","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111999144","display_name":"Shanshan Dai","orcid":null},"institutions":[{"id":"https://openalex.org/I111088046","display_name":"Boston University","ror":"https://ror.org/05qwgg493","country_code":"US","type":"education","lineage":["https://openalex.org/I111088046"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shanshan Dai","raw_affiliation_strings":["Boston University, Boston, MA, US","Dept. of Electr. & Comput. Eng., Boston Univ., Boston, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Boston University, Boston, MA, US","institution_ids":["https://openalex.org/I111088046"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Boston Univ., Boston, MA, USA","institution_ids":["https://openalex.org/I111088046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013593283","display_name":"Xiaofei Cao","orcid":"https://orcid.org/0000-0001-8836-659X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaofei Cao","raw_affiliation_strings":["State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100681724","display_name":"Ting Yi","orcid":"https://orcid.org/0000-0002-9960-3746"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ting Yi","raw_affiliation_strings":["State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111816021","display_name":"Allyn E. Hubbard","orcid":null},"institutions":[{"id":"https://openalex.org/I111088046","display_name":"Boston University","ror":"https://ror.org/05qwgg493","country_code":"US","type":"education","lineage":["https://openalex.org/I111088046"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Allyn E. Hubbard","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Boston University, MA, USA","Dept. of Electr. & Comput. Eng., Boston Univ., Boston, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Boston University, MA, USA","institution_ids":["https://openalex.org/I111088046"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Boston Univ., Boston, MA, USA","institution_ids":["https://openalex.org/I111088046"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082092557","display_name":"Zhiliang Hong","orcid":"https://orcid.org/0000-0002-9968-5964"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiliang Hong","raw_affiliation_strings":["State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4497,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.80431952,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"21","issue":"10","first_page":"1928","last_page":"1935"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transconductance","display_name":"Transconductance","score":0.8904455304145813},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.7170538306236267},{"id":"https://openalex.org/keywords/operational-transconductance-amplifier","display_name":"Operational transconductance amplifier","score":0.689483642578125},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.6004483103752136},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5857462286949158},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5208673477172852},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.47618499398231506},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.4745422303676605},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41202154755592346},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.352944552898407},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.33802956342697144},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.3283599019050598},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2949623167514801},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11256438493728638},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07845962047576904}],"concepts":[{"id":"https://openalex.org/C2779283907","wikidata":"https://www.wikidata.org/wiki/Q1632964","display_name":"Transconductance","level":4,"score":0.8904455304145813},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.7170538306236267},{"id":"https://openalex.org/C58117264","wikidata":"https://www.wikidata.org/wiki/Q1239595","display_name":"Operational transconductance amplifier","level":5,"score":0.689483642578125},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.6004483103752136},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5857462286949158},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5208673477172852},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.47618499398231506},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.4745422303676605},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41202154755592346},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.352944552898407},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.33802956342697144},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3283599019050598},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2949623167514801},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11256438493728638},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07845962047576904}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2012.2220387","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2220387","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.699999988079071}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310145","display_name":"Johns Hopkins University","ror":"https://ror.org/00za53h95"},{"id":"https://openalex.org/F4320321851","display_name":"Fudan University","ror":"https://ror.org/013q1eq08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1500845134","https://openalex.org/W1733919024","https://openalex.org/W1965367876","https://openalex.org/W2010266312","https://openalex.org/W2030605186","https://openalex.org/W2059188567","https://openalex.org/W2065161569","https://openalex.org/W2080615209","https://openalex.org/W2101237940","https://openalex.org/W2101809138","https://openalex.org/W2108613929","https://openalex.org/W2110276082","https://openalex.org/W2114490265","https://openalex.org/W2140281076","https://openalex.org/W2141266255","https://openalex.org/W2151589511","https://openalex.org/W2159297635"],"related_works":["https://openalex.org/W2547382822","https://openalex.org/W2187192882","https://openalex.org/W3042692986","https://openalex.org/W2056901472","https://openalex.org/W1833617297","https://openalex.org/W1015795869","https://openalex.org/W2093515901","https://openalex.org/W3182671744","https://openalex.org/W2108915325","https://openalex.org/W1548186132"],"abstract_inverted_index":{"A":[0],"low-power":[1],"process-independent":[2],"programmable":[3,58,75],"transconductance":[4,15,21],"rail-to-rail":[5],"operational":[6],"amplifier":[7],"(OpAmp)":[8],"is":[9,113],"proposed.":[10],"It":[11],"employs":[12],"an":[13],"improved":[14],"feedback":[16],"loop":[17],"that":[18],"senses":[19],"the":[20,35,81,110],"(g":[22],"<sub":[23,60],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[24,61],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">mT</sub>":[25,62],")":[26],"accurately":[27],"and":[28,74],"enforces":[29],"it":[30],"to":[31,34,66],"be":[32],"equal":[33],"conductance":[36],"of":[37,72,90,102,107,109],"a":[38,44,51,56,87,94],"reference":[39,82],"resistor.":[40],"Experimental":[41],"results":[42],"in":[43],"0.13-":[45],"\u03bcm":[46],"standard":[47],"CMOS":[48],"technology":[49],"under":[50],"1-V":[52],"power":[53],"supply":[54],"demonstrate":[55],"continuous":[57],"g":[59],"range":[63],"from":[64,80],"87":[65],"165":[67],"\u03bcA/V":[68],"with":[69,93],"minimum":[70],"fluctuation":[71],"\u00b12.4%":[73],"deviation":[76],"less":[77],"than":[78],"4.5%":[79],"value.":[83],"The":[84,105],"OpAmp":[85,112],"achieves":[86],"unity-gain":[88],"bandwidth":[89],"3.7":[91],"MHz":[92],"95-pF":[95],"load":[96],"while":[97],"only":[98],"consuming":[99],"187":[100],"\u03bcA":[101],"quiescent":[103],"current.":[104],"figure":[106],"merit":[108],"proposed":[111],"1879":[114],"MHz\u00b7pF/mA.":[115]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}