{"id":"https://openalex.org/W2170706925","doi":"https://doi.org/10.1109/tvlsi.2012.2210451","title":"IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test","display_name":"IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test","publication_year":2012,"publication_date":"2012-08-28","ids":{"openalex":"https://openalex.org/W2170706925","doi":"https://doi.org/10.1109/tvlsi.2012.2210451","mag":"2170706925"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2012.2210451","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2210451","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082268567","display_name":"Katherine Shu-Min Li","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Katherine Shu-Min Li","raw_affiliation_strings":["Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076303510","display_name":"Yi-Yu Liao","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Yu Liao","raw_affiliation_strings":["Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5082268567"],"corresponding_institution_ids":["https://openalex.org/I142974352"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.1768784,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"21","issue":"7","first_page":"1333","last_page":"1337"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7365943789482117},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6400230526924133},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5608221292495728},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5038761496543884},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4964810013771057},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.47143688797950745},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4601495862007141},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.4527462124824524},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.45111751556396484},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4322243928909302},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4215081036090851},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.4201606512069702},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3736898899078369},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3566475212574005},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.262479305267334},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.1974429190158844},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.15780261158943176},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.12518325448036194},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11093175411224365},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08937549591064453}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7365943789482117},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6400230526924133},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5608221292495728},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5038761496543884},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4964810013771057},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.47143688797950745},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4601495862007141},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.4527462124824524},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.45111751556396484},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4322243928909302},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4215081036090851},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.4201606512069702},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3736898899078369},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3566475212574005},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.262479305267334},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.1974429190158844},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.15780261158943176},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.12518325448036194},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11093175411224365},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08937549591064453},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2012.2210451","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2210451","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1511158165","https://openalex.org/W1583788531","https://openalex.org/W1975628451","https://openalex.org/W2009282987","https://openalex.org/W2040265583","https://openalex.org/W2049458920","https://openalex.org/W2077251002","https://openalex.org/W2100158488","https://openalex.org/W2162281676","https://openalex.org/W2162877164","https://openalex.org/W2168114925","https://openalex.org/W4248596413","https://openalex.org/W6684332989"],"related_works":["https://openalex.org/W2165948443","https://openalex.org/W2106258585","https://openalex.org/W2108140302","https://openalex.org/W2139513292","https://openalex.org/W4251092725","https://openalex.org/W2989178840","https://openalex.org/W2120517966","https://openalex.org/W2061326683","https://openalex.org/W2384601745","https://openalex.org/W2130496378"],"abstract_inverted_index":{"On-chip":[0],"interconnect":[1,30],"structures":[2],"become":[3],"much":[4],"more":[5],"complicated":[6],"and":[7,32,41,90],"dominate":[8],"system":[9],"performance":[10],"in":[11,28],"multicore":[12],"system-on-chips.":[13],"Oscillation":[14],"ring":[15,72],"(OR)":[16],"test":[17,21,56,63,88,95,119],"is":[18,57,97],"an":[19],"efficient":[20],"method":[22],"for":[23,46],"most":[24],"types":[25],"of":[26,54,62,94],"faults":[27],"the":[29,42,60,69,86,92,117],"structures,":[31],"previous":[33],"studies":[34],"show":[35],"that":[36,80,110,116],"both":[37],"100%":[38],"fault":[39,48],"coverage":[40],"optimum":[43],"diagnosis":[44],"resolution":[45],"various":[47],"models":[49],"are":[50],"achievable.":[51],"The":[52],"cost":[53],"OR":[55],"decided":[58],"by":[59],"number":[61,93],"sessions":[64,96],"required":[65],"to":[66,76,107],"form":[67],"all":[68],"rings.":[70],"Previous":[71],"generation":[73],"algorithm":[74],"tries":[75],"generate":[77,108],"long":[78],"rings":[79,109],"usually":[81],"cannot":[82],"be":[83,112,122],"put":[84],"into":[85],"same":[87],"session,":[89],"thus":[91],"not":[98],"necessarily":[99],"smaller.":[100],"In":[101],"this":[102],"brief,":[103],"we":[104],"study":[105],"techniques":[106],"can":[111,121],"tested":[113],"concurrently,":[114],"so":[115],"overall":[118],"time":[120],"reduced":[123],"significantly.":[124]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}