{"id":"https://openalex.org/W2155021765","doi":"https://doi.org/10.1109/tvlsi.2012.2210256","title":"Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes","display_name":"Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes","publication_year":2012,"publication_date":"2012-08-29","ids":{"openalex":"https://openalex.org/W2155021765","doi":"https://doi.org/10.1109/tvlsi.2012.2210256","mag":"2155021765"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2012.2210256","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2210256","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065412990","display_name":"Yangyang Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yangyang Pan","raw_affiliation_strings":["Department of Electrical, Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053635255","display_name":"Guiqiang Dong","orcid":null},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Guiqiang Dong","raw_affiliation_strings":["Department of Electrical, Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100378792","display_name":"Tong Zhang","orcid":"https://orcid.org/0000-0002-5511-2558"},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tong Zhang","raw_affiliation_strings":["Department of Electrical, Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5065412990"],"corresponding_institution_ids":["https://openalex.org/I165799507"],"apc_list":null,"apc_paid":null,"fwci":3.7606,"has_fulltext":false,"cited_by_count":58,"citation_normalized_percentile":{"value":0.93859513,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"21","issue":"7","first_page":"1350","last_page":"1354"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9853000044822693,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6660977005958557},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6041924953460693},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5780953764915466},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.44665640592575073},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4294436275959015},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4280295670032501},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3751814365386963},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.37305375933647156},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37212634086608887},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3354482054710388},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2939609885215759},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1652263104915619},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12418204545974731}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6660977005958557},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6041924953460693},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5780953764915466},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.44665640592575073},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4294436275959015},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4280295670032501},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3751814365386963},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37305375933647156},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37212634086608887},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3354482054710388},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2939609885215759},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1652263104915619},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12418204545974731},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2012.2210256","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2210256","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1495548585","https://openalex.org/W1526462389","https://openalex.org/W1963830244","https://openalex.org/W1983978460","https://openalex.org/W2036382651","https://openalex.org/W2095342970","https://openalex.org/W2099753358","https://openalex.org/W2109190450","https://openalex.org/W2115009671","https://openalex.org/W2132992589","https://openalex.org/W2165068957","https://openalex.org/W2917663763","https://openalex.org/W6629619863","https://openalex.org/W6684515133"],"related_works":["https://openalex.org/W2086578073","https://openalex.org/W2537420636","https://openalex.org/W2036350002","https://openalex.org/W2076885774","https://openalex.org/W2970146629","https://openalex.org/W1903254700","https://openalex.org/W1807198022","https://openalex.org/W1969077618","https://openalex.org/W1965767061","https://openalex.org/W1977078557"],"abstract_inverted_index":{"This":[0,67],"brief":[1,68],"presents":[2,69],"a":[3,50,70],"NAND":[4,23],"Flash":[5,24],"memory":[6,12,25,46,84,91],"wear-leveling":[7,26,74,99,113],"algorithm":[8,75],"that":[9,76],"explicitly":[10],"uses":[11,77],"raw":[13],"bit":[14],"error":[15],"rate":[16],"(BER)":[17],"as":[18,57,80],"the":[19,32,38,45,64,81,98],"optimization":[20],"target.":[21],"Although":[22],"has":[27],"been":[28,103],"well":[29],"studied,":[30],"all":[31,44],"existing":[33,112],"algorithms":[34],"aim":[35],"to":[36,95,106],"equalize":[37],"number":[39],"of":[40,83],"programming/erase":[41],"cycles":[42],"among":[43],"blocks.":[47],"Unfortunately,":[48],"such":[49],"conventional":[51],"design":[52],"practice":[53],"becomes":[54,60],"increasingly":[55,61],"suboptimal":[56],"inter-block":[58],"variation":[59],"significant":[62],"with":[63],"technology":[65],"scaling.":[66],"dynamic":[71,90],"BER-based":[72],"greedy":[73],"BER":[78],"statistics":[79],"measurement":[82],"block":[85,92],"wear-out":[86],"pace,":[87],"and":[88],"guides":[89],"data":[93],"swapping":[94],"fully":[96],"maximize":[97],"efficiency.":[100],"Simulations":[101],"have":[102],"carried":[104],"out":[105],"quantitatively":[107],"demonstrate":[108],"its":[109],"advantages":[110],"over":[111],"algorithms.":[114]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":8},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":9},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":3}],"updated_date":"2026-03-27T14:29:43.386196","created_date":"2025-10-10T00:00:00"}
