{"id":"https://openalex.org/W2018430360","doi":"https://doi.org/10.1109/tvlsi.2012.2204782","title":"Asynchronous Fine-Grain Power-Gated Logic","display_name":"Asynchronous Fine-Grain Power-Gated Logic","publication_year":2012,"publication_date":"2012-07-10","ids":{"openalex":"https://openalex.org/W2018430360","doi":"https://doi.org/10.1109/tvlsi.2012.2204782","mag":"2018430360"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2012.2204782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2204782","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102063487","display_name":"Meng\u2010Chou Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I70522481","display_name":"National Changhua University of Education","ror":"https://ror.org/005gkfa10","country_code":"TW","type":"education","lineage":["https://openalex.org/I70522481"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Meng-Chou Chang","raw_affiliation_strings":["Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan","Dept. of Electron. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan","institution_ids":["https://openalex.org/I70522481"]},{"raw_affiliation_string":"Dept. of Electron. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan","institution_ids":["https://openalex.org/I70522481"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068541288","display_name":"Wei\u2010Hsiang Chang","orcid":"https://orcid.org/0000-0002-4001-8382"},"institutions":[{"id":"https://openalex.org/I70522481","display_name":"National Changhua University of Education","ror":"https://ror.org/005gkfa10","country_code":"TW","type":"education","lineage":["https://openalex.org/I70522481"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Hsiang Chang","raw_affiliation_strings":["Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan","Dept. of Electron. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan","institution_ids":["https://openalex.org/I70522481"]},{"raw_affiliation_string":"Dept. of Electron. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan","institution_ids":["https://openalex.org/I70522481"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I70522481"],"apc_list":null,"apc_paid":null,"fwci":2.2098,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.88388681,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"21","issue":"6","first_page":"1143","last_page":"1153"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7222588658332825},{"id":"https://openalex.org/keywords/handshake","display_name":"Handshake","score":0.709296464920044},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.46236732602119446},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.41636204719543457},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.3768027126789093},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.30479347705841064},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19356447458267212},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13816601037979126}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7222588658332825},{"id":"https://openalex.org/C2778000800","wikidata":"https://www.wikidata.org/wiki/Q830043","display_name":"Handshake","level":3,"score":0.709296464920044},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.46236732602119446},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.41636204719543457},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.3768027126789093},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.30479347705841064},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19356447458267212},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13816601037979126}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2012.2204782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2204782","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1582019256","https://openalex.org/W1592564914","https://openalex.org/W1594470711","https://openalex.org/W1996005423","https://openalex.org/W2015111322","https://openalex.org/W2045383911","https://openalex.org/W2048874455","https://openalex.org/W2056796532","https://openalex.org/W2076469371","https://openalex.org/W2083626899","https://openalex.org/W2098194061","https://openalex.org/W2099019121","https://openalex.org/W2106379279","https://openalex.org/W2114621701","https://openalex.org/W2122846829","https://openalex.org/W2122984966","https://openalex.org/W2131862714","https://openalex.org/W2133630856","https://openalex.org/W2134127605","https://openalex.org/W2136486818","https://openalex.org/W2138093253","https://openalex.org/W2143378652","https://openalex.org/W2147597268","https://openalex.org/W2148916286","https://openalex.org/W2150526221","https://openalex.org/W2160715044","https://openalex.org/W2166756725","https://openalex.org/W2168281491","https://openalex.org/W2170444169","https://openalex.org/W2487142227","https://openalex.org/W4251240676","https://openalex.org/W4253620068","https://openalex.org/W4285719527","https://openalex.org/W6635440050","https://openalex.org/W6675974091","https://openalex.org/W6683384013"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2526300902","https://openalex.org/W2170504327","https://openalex.org/W1977171228","https://openalex.org/W2121963733","https://openalex.org/W2766377030","https://openalex.org/W2542337934","https://openalex.org/W2041787842","https://openalex.org/W1985308002"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,39],"novel":[4],"low-power":[5],"logic":[6,12,27,33],"family,":[7],"called":[8,153],"asynchronous":[9],"fine-grain":[10],"power-gated":[11],"(AFPL).":[13],"Each":[14],"pipeline":[15,181],"stage":[16],"in":[17,95,155,164],"the":[18,32,36,46,53,57,96,100,105,108,116,124,135,141,168,179,185,189],"AFPL":[19,58,97,190],"circuit":[20,195],"is":[21],"comprised":[22],"of":[23,35,104,111,127,143,188,194],"efficient":[24],"charge":[25,88,106,123],"recovery":[26],"(ECRL)":[28],"gates,":[29],"which":[30,42],"implement":[31],"function":[34],"stage,":[37],"and":[38,49,64,72,79],"handshake":[40,157],"controller,":[41],"handles":[43],"handshaking":[44],"with":[45],"neighboring":[47],"stages":[48],"provides":[50],"power":[51,63,84],"to":[52,122,132,139],"ECRL":[54,60,74,113,129,145,162],"gates.":[55],"In":[56],"circuit,":[59,191],"gates":[61,75],"acquire":[62],"become":[65],"active":[66],"only":[67],"when":[68],"performing":[69],"useful":[70],"computations,":[71],"idle":[73],"are":[76],"not":[77],"powered":[78],"thus":[80],"have":[81,197],"negligible":[82],"leakage":[83],"dissipation.":[85],"The":[86],"partial":[87],"reuse":[89],"(PCR)":[90],"mechanism":[91],"can":[92,119,166],"be":[93,120],"incorporated":[94],"circuit.":[98],"With":[99],"PCR":[101],"mechanism,":[102],"part":[103],"on":[107],"output":[109,125,174],"nodes":[110,126],"an":[112,144,150,161],"gate":[114,130,163],"entering":[115],"discharge":[117],"phase":[118],"reused":[121],"another":[128],"about":[131],"evaluate,":[133],"reducing":[134],"energy":[136],"dissipation":[137],"required":[138],"complete":[140],"evaluation":[142],"gate.":[146],"Moreover,":[147],"AFPL-PCR":[148,165],"adopts":[149],"enhanced":[151],"C-element,":[152],"C*-element,":[154],"its":[156,173],"controllers":[158],"such":[159],"that":[160],"enter":[167],"sleep":[169],"mode":[170],"early":[171],"once":[172],"has":[175],"been":[176,198],"received":[177],"by":[178],"downstream":[180],"stage.":[182],"To":[183],"mitigate":[184],"hardware":[186],"overhead":[187],"two":[192],"techniques":[193],"simplification":[196],"developed.":[199]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":8}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
