{"id":"https://openalex.org/W2111435398","doi":"https://doi.org/10.1109/tvlsi.2012.2202700","title":"Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory","display_name":"Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory","publication_year":2012,"publication_date":"2012-07-24","ids":{"openalex":"https://openalex.org/W2111435398","doi":"https://doi.org/10.1109/tvlsi.2012.2202700","mag":"2111435398"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2012.2202700","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2202700","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066534595","display_name":"Jingtong Hu","orcid":"https://orcid.org/0000-0003-4029-4034"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jingtong Hu","raw_affiliation_strings":["Department of Computer Science, University of Texas, Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101441768","display_name":"Chun Jason Xue","orcid":"https://orcid.org/0000-0002-6431-9868"},"institutions":[{"id":"https://openalex.org/I168719708","display_name":"City University of Hong Kong","ror":"https://ror.org/03q8dnn23","country_code":"HK","type":"education","lineage":["https://openalex.org/I168719708"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Chun Jason Xue","raw_affiliation_strings":["Department of Computer Science, City University of Hong Kong, Hong Kong, China"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, City University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I168719708"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005358696","display_name":"Qingfeng Zhuge","orcid":"https://orcid.org/0000-0002-1107-3470"},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qingfeng Zhuge","raw_affiliation_strings":["College of Computer Science and Engineering, Chongqing University, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"College of Computer Science and Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005054852","display_name":"Wei-Che Tseng","orcid":"https://orcid.org/0009-0003-4405-8239"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei-Che Tseng","raw_affiliation_strings":["Department of Computer Science, University of Texas, Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077381252","display_name":"Edwin H.\u2010M. Sha","orcid":"https://orcid.org/0000-0001-5605-5631"},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]},{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["CN","US"],"is_corresponding":false,"raw_author_name":"Edwin H.-M. Sha","raw_affiliation_strings":["College of Computer Science and Engineering, Chongqing University, Chongqing, China","Department of Computer Science, University of Texas, Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"College of Computer Science and Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]},{"raw_affiliation_string":"Department of Computer Science, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5066534595"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":5.8012,"has_fulltext":false,"cited_by_count":61,"citation_normalized_percentile":{"value":0.96505527,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"21","issue":"6","first_page":"1094","last_page":"1102"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8340187072753906},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6599926352500916},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.6358180046081543},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6198248267173767},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5924167633056641},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.5552359819412231},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5442433953285217},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5335401296615601},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.4835531413555145},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4754999577999115},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.47213107347488403},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.46820786595344543},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.46454644203186035},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.46189606189727783},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4327370226383209},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.420474112033844},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40186750888824463},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3983234763145447},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3274664282798767},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.28018918633461},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.2486501932144165},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1783187985420227},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12375226616859436}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8340187072753906},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6599926352500916},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.6358180046081543},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6198248267173767},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5924167633056641},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.5552359819412231},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5442433953285217},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5335401296615601},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.4835531413555145},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4754999577999115},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.47213107347488403},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.46820786595344543},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.46454644203186035},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.46189606189727783},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4327370226383209},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.420474112033844},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40186750888824463},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3983234763145447},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3274664282798767},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.28018918633461},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.2486501932144165},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1783187985420227},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12375226616859436},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2012.2202700","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2202700","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":48,"referenced_works":["https://openalex.org/W1492553566","https://openalex.org/W1686420892","https://openalex.org/W1816728452","https://openalex.org/W1976386267","https://openalex.org/W1977857710","https://openalex.org/W1984418330","https://openalex.org/W1989660200","https://openalex.org/W2005777829","https://openalex.org/W2058668353","https://openalex.org/W2058815081","https://openalex.org/W2064977311","https://openalex.org/W2078431215","https://openalex.org/W2086329118","https://openalex.org/W2086804599","https://openalex.org/W2092627171","https://openalex.org/W2096259250","https://openalex.org/W2096648046","https://openalex.org/W2096800126","https://openalex.org/W2099798359","https://openalex.org/W2099856791","https://openalex.org/W2102449048","https://openalex.org/W2104070819","https://openalex.org/W2116826022","https://openalex.org/W2132389101","https://openalex.org/W2135393827","https://openalex.org/W2140144029","https://openalex.org/W2144351373","https://openalex.org/W2147720557","https://openalex.org/W2148831941","https://openalex.org/W2149590159","https://openalex.org/W2156159026","https://openalex.org/W2162528816","https://openalex.org/W2163545127","https://openalex.org/W2543205889","https://openalex.org/W3143415687","https://openalex.org/W4231378725","https://openalex.org/W4237860043","https://openalex.org/W4238826965","https://openalex.org/W4241166746","https://openalex.org/W4243973767","https://openalex.org/W4244361616","https://openalex.org/W6637151178","https://openalex.org/W6638634483","https://openalex.org/W6672035706","https://openalex.org/W6674323626","https://openalex.org/W6681143753","https://openalex.org/W6681706910","https://openalex.org/W6682917345"],"related_works":["https://openalex.org/W4238754064","https://openalex.org/W4293159259","https://openalex.org/W2151951695","https://openalex.org/W3093911585","https://openalex.org/W1575240748","https://openalex.org/W4389371524","https://openalex.org/W2546565930","https://openalex.org/W2534610203","https://openalex.org/W2579594055","https://openalex.org/W3090254958"],"abstract_inverted_index":{"Embedded":[0],"systems":[1,39],"normally":[2],"have":[3],"a":[4,28,66,73,83,167],"tight":[5],"energy":[6,20,156],"budget.":[7],"Since":[8],"the":[9,16,51,54,102,124,131,135,138,141,148,154,160,173],"on-chip":[10,30],"cache":[11],"typically":[12],"consumes":[13],"25%-50%":[14],"of":[15,53,76,89,101,109,123,127,137],"processor's":[17],"area":[18,44],"and":[19,45,94,106,159],"consumption,":[21],"scratch":[22],"pad":[23],"memory":[24,70,92,96,149],"(SPM),":[25],"which":[26,87],"is":[27,64,117],"software-controlled":[29],"memory,":[31],"has":[32],"been":[33],"widely":[34],"adopted":[35],"in":[36],"many":[37],"embedded":[38],"due":[40],"to":[41,98,120,130],"its":[42],"smaller":[43],"lower":[46],"power":[47,62,105,162],"consumption.":[48],"However,":[49],"as":[50],"speed":[52],"CMOS":[55],"transistors":[56],"increases":[57],"along":[58],"with":[59,72,134,166,172],"density,":[60],"leakage":[61,104,161],"consumption":[63],"becoming":[65],"critical":[67],"issue":[68],"for":[69],"components":[71],"large":[74],"number":[75],"transistors.":[77],"In":[78],"this":[79],"paper,":[80],"we":[81],"propose":[82],"novel":[84,112,142],"hybrid":[85,143],"SPM":[86,144,171],"consists":[88],"static":[90],"random-access":[91],"(SRAM)":[93],"nonvolatile":[95],"(NVM)":[97],"take":[99],"advantage":[100],"ultralow":[103],"high":[107],"density":[108],"latter.":[110],"A":[111],"dynamic":[113,155],"data":[114],"management":[115],"algorithm":[116],"also":[118],"proposed":[119,139],"make":[121],"use":[122],"full":[125],"potential":[126],"NVM.":[128],"According":[129],"experimental":[132],"results,":[133],"help":[136],"algorithm,":[140],"architecture":[145],"can":[146],"reduce":[147],"access":[150],"time":[151],"by":[152,157,163],"18.17%,":[153],"24.29%,":[158],"37.34%":[164],"compared":[165],"baseline":[168],"pure":[169],"SRAM":[170],"same":[174],"area.":[175]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":10},{"year":2015,"cited_by_count":10},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}