{"id":"https://openalex.org/W2124352950","doi":"https://doi.org/10.1109/tvlsi.2012.2187689","title":"Power-Up Sequence Control for MTCMOS Designs","display_name":"Power-Up Sequence Control for MTCMOS Designs","publication_year":2012,"publication_date":"2012-03-19","ids":{"openalex":"https://openalex.org/W2124352950","doi":"https://doi.org/10.1109/tvlsi.2012.2187689","mag":"2124352950"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2012.2187689","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2187689","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055000437","display_name":"Shihao Chen","orcid":"https://orcid.org/0000-0001-7646-8003"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]},{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shi-Hao Chen","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","Design Service Division, Global Unichip Corporation, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Design Service Division, Global Unichip Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071624937","display_name":"Youn-Long Lin","orcid":"https://orcid.org/0000-0002-4106-8082"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Youn-Long Lin","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045156360","display_name":"Mango C.-T. Chao","orcid":"https://orcid.org/0000-0002-7299-9015"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mango C.-T. Chao","raw_affiliation_strings":["Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2492,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.82477934,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"21","issue":"3","first_page":"413","last_page":"423"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.7208125591278076},{"id":"https://openalex.org/keywords/inrush-current","display_name":"Inrush current","score":0.7145578265190125},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.6079782247543335},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.5520305633544922},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5518843531608582},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5350314974784851},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4803398847579956},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4767766296863556},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4714401960372925},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.45814579725265503},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.39681869745254517},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3510529398918152},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2517249286174774},{"id":"https://openalex.org/keywords/transformer","display_name":"Transformer","score":0.06988057494163513}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.7208125591278076},{"id":"https://openalex.org/C23340480","wikidata":"https://www.wikidata.org/wiki/Q358932","display_name":"Inrush current","level":4,"score":0.7145578265190125},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.6079782247543335},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.5520305633544922},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5518843531608582},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5350314974784851},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4803398847579956},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4767766296863556},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4714401960372925},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.45814579725265503},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.39681869745254517},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3510529398918152},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2517249286174774},{"id":"https://openalex.org/C66322947","wikidata":"https://www.wikidata.org/wiki/Q11658","display_name":"Transformer","level":3,"score":0.06988057494163513},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2012.2187689","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2187689","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.899.97","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.899.97","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"https://ir.nctu.edu.tw:443/bitstream/11536/21178/1/000315639900002.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1582019256","https://openalex.org/W2004934210","https://openalex.org/W2017322750","https://openalex.org/W2019592163","https://openalex.org/W2030183102","https://openalex.org/W2065980112","https://openalex.org/W2101293217","https://openalex.org/W2102740661","https://openalex.org/W2104042042","https://openalex.org/W2115403662","https://openalex.org/W2122006764","https://openalex.org/W2126416778","https://openalex.org/W2143372315","https://openalex.org/W2151477922","https://openalex.org/W2156240767","https://openalex.org/W2156805339","https://openalex.org/W2160457997","https://openalex.org/W2162051978","https://openalex.org/W2364237620","https://openalex.org/W4233553716","https://openalex.org/W4236524207","https://openalex.org/W4246982917","https://openalex.org/W4247881338","https://openalex.org/W6655081566","https://openalex.org/W6675360586","https://openalex.org/W6675643309","https://openalex.org/W6680958425"],"related_works":["https://openalex.org/W1537780284","https://openalex.org/W2599764483","https://openalex.org/W2078514087","https://openalex.org/W2061209405","https://openalex.org/W3061280797","https://openalex.org/W2063621092","https://openalex.org/W3015448157","https://openalex.org/W4312057941","https://openalex.org/W2124352950","https://openalex.org/W2331459838"],"abstract_inverted_index":{"Power":[0],"gating":[1],"is":[2,35],"effective":[3],"for":[4,55,95],"reducing":[5,79,123],"standby":[6],"leakage":[7],"power":[8,145],"as":[9],"multi-threshold":[10],"CMOS":[11],"(MTCMOS)":[12],"designs":[13,105,139],"have":[14],"become":[15],"popular":[16],"in":[17,43,113,136],"the":[18,62,66,75,80,85,97,107,110,115,119,124,131,134],"industry.":[19],"However,":[20],"a":[21,32,52,57,70,91],"large":[22],"inrush":[23,67,116],"current":[24,68],"and":[25,78,122,147],"dynamic":[26,81,125],"IR":[27,82,126],"drop":[28,83],"may":[29],"occur":[30],"when":[31],"circuit":[33,48,94],"domain":[34,72],"powered":[36],"up":[37],"with":[38,140],"MTCMOS":[39],"switches.":[40],"This":[41],"could":[42],"turn":[44],"lead":[45],"to":[46,64],"improper":[47],"operation.":[49],"We":[50,88],"propose":[51,90],"novel":[53],"framework":[54,112,135],"generating":[56],"proper":[58],"power-up":[59,76,120],"sequence":[60],"of":[61,69,84,109,133],"switches":[63,146],"control":[65],"power-gated":[71],"while":[73],"minimizing":[74,118],"time":[77],"active":[86],"domains.":[87],"also":[89],"configurable":[92],"domino-delay":[93],"implementing":[96],"sequence.":[98],"Experimental":[99],"results":[100],"based":[101],"on":[102],"state-of-the-art":[103],"industrial":[104],"demonstrate":[106],"effectiveness":[108],"proposed":[111],"limiting":[114],"current,":[117],"time,":[121],"drop.":[127],"Results":[128],"further":[129],"confirm":[130],"efficiency":[132],"handling":[137],"large-scale":[138],"more":[141],"than":[142],"80":[143],"K":[144],"100":[148],"M":[149],"transistors.":[150]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
