{"id":"https://openalex.org/W1964410717","doi":"https://doi.org/10.1109/tvlsi.2012.2187543","title":"In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis","display_name":"In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis","publication_year":2012,"publication_date":"2012-03-08","ids":{"openalex":"https://openalex.org/W1964410717","doi":"https://doi.org/10.1109/tvlsi.2012.2187543","mag":"1964410717"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2012.2187543","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2187543","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072830508","display_name":"Jhih-Wei You","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jhih-Wei You","raw_affiliation_strings":["Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085636078","display_name":"Shi\u2010Yu Huang","orcid":"https://orcid.org/0000-0002-3721-987X"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shi-Yu Huang","raw_affiliation_strings":["Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110832349","display_name":"Yu-Hsiang Lin","orcid":"https://orcid.org/0000-0003-0581-257X"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Hsiang Lin","raw_affiliation_strings":["Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012711139","display_name":"Meng-Hsiu Tsai","orcid":"https://orcid.org/0009-0008-8578-4428"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Meng-Hsiu Tsai","raw_affiliation_strings":["Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084103721","display_name":"Ding-Ming Kwai","orcid":"https://orcid.org/0000-0001-7769-7879"},"institutions":[{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ding-Ming Kwai","raw_affiliation_strings":["Information and Communication Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Information and Communication Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113501237","display_name":"Yung-Fa Chou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Fa Chou","raw_affiliation_strings":["Industrial Technology Research Institute, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Industrial Technology Research Institute, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075548524","display_name":"Cheng\u2010Wen Wu","orcid":"https://orcid.org/0000-0001-8614-7908"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]},{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Cheng-Wen Wu","raw_affiliation_strings":["Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan","Information and Communication Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Information and Communication Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.9987,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.8683503,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"21","issue":"3","first_page":"443","last_page":"453"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.7231274843215942},{"id":"https://openalex.org/keywords/oscillation","display_name":"Oscillation (cell signaling)","score":0.6416416764259338},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6120302677154541},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6083189249038696},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.5928804874420166},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5406491160392761},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.46757203340530396},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46754470467567444},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4530279040336609},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4407024383544922},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.39133599400520325},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3454968333244324},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3039408028125763},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.20554697513580322},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19295945763587952}],"concepts":[{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.7231274843215942},{"id":"https://openalex.org/C2778439541","wikidata":"https://www.wikidata.org/wiki/Q7106412","display_name":"Oscillation (cell signaling)","level":2,"score":0.6416416764259338},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6120302677154541},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6083189249038696},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.5928804874420166},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5406491160392761},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.46757203340530396},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46754470467567444},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4530279040336609},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4407024383544922},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.39133599400520325},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3454968333244324},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3039408028125763},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.20554697513580322},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19295945763587952},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2012.2187543","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2187543","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1583788531","https://openalex.org/W1996050875","https://openalex.org/W2009282987","https://openalex.org/W2013560002","https://openalex.org/W2055841712","https://openalex.org/W2061584132","https://openalex.org/W2064712157","https://openalex.org/W2095790208","https://openalex.org/W2115150721","https://openalex.org/W2122592588","https://openalex.org/W2122750932","https://openalex.org/W2132155220","https://openalex.org/W2133276614","https://openalex.org/W2140711812","https://openalex.org/W2143875880","https://openalex.org/W2155707315","https://openalex.org/W3144072891","https://openalex.org/W4236637407","https://openalex.org/W4245501382","https://openalex.org/W6677325421","https://openalex.org/W6680984798"],"related_works":["https://openalex.org/W3165307257","https://openalex.org/W2515312339","https://openalex.org/W2145098804","https://openalex.org/W4226211266","https://openalex.org/W2991151827","https://openalex.org/W2130440338","https://openalex.org/W1574518580","https://openalex.org/W2791832526","https://openalex.org/W2161229876","https://openalex.org/W4361799621"],"abstract_inverted_index":{"In":[0,84],"this":[1,85],"paper,":[2],"we":[3,60,87,128],"propose":[4],"a":[5,23,62,153,156,190],"method":[6],"and":[7,96,182],"the":[8,13,17,53,57,70,89,92,104,107,115,136,176,180,183,187],"required":[9],"architecture":[10,132],"for":[11],"characterizing":[12],"propagation":[14,71,116,184],"delays":[15,185],"of":[16,27,56,73,91,103,106,118,126,140,147,186],"through":[18],"Silicon":[19],"vias":[20],"(TSVs)":[21],"in":[22,78,101,155],"3-D":[24,191],"IC.":[25,192],"First":[26],"all,":[28],"every":[29],"two":[30,93,148],"TSVs":[31,149,188],"are":[32],"paired":[33],"up":[34],"to":[35,67,178],"form":[36],"an":[37,79,131],"oscillation":[38,54,80,108],"ring":[39],"with":[40],"some":[41,112],"peripheral":[42],"circuits.":[43],"Their":[44],"joint":[45],"performance":[46,137],"can":[47,121,134,174],"thus":[48],"be":[49,122],"measured":[50],"roughly":[51],"by":[52,171],"period":[55],"ring.":[58],"Next,":[59],"utilize":[61],"technique":[63],"called":[64],"sensitivity":[65],"analysis":[66],"further":[68],"derive":[69],"delay":[72,117],"each":[74,119,141],"individual":[75],"TSV":[76,94,120],"participating":[77],"ring-a":[81],"distilling":[82],"process.":[83],"process,":[86],"perturb":[88],"strength":[90],"drivers,":[95],"then":[97],"measure":[98],"their":[99],"effects":[100],"terms":[102],"change":[105],"ring's":[109],"period.":[110],"By":[111],"following":[113],"analysis,":[114],"revealed.":[123],"On":[124],"top":[125],"scheme,":[127],"also":[129],"present":[130],"that":[133,145],"activate":[135],"characterization":[138],"process":[139],"test":[142],"unit":[143],"-":[144,150],"consists":[146],"one":[151,173],"at":[152],"time":[154],"proper":[157],"sequence.":[158],"The":[159],"area":[160],"overhead":[161],"is":[162],"only":[163],"18.97":[164],"equivalent":[165],"two-input":[166],"NAND":[167],"gate":[168],"per":[169],"TSV,":[170],"which":[172],"gain":[175],"ability":[177],"profile":[179],"capacitances":[181],"on":[189]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
