{"id":"https://openalex.org/W1994898876","doi":"https://doi.org/10.1109/tvlsi.2012.2186989","title":"A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering","display_name":"A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering","publication_year":2012,"publication_date":"2012-03-08","ids":{"openalex":"https://openalex.org/W1994898876","doi":"https://doi.org/10.1109/tvlsi.2012.2186989","mag":"1994898876"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2012.2186989","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2186989","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007788756","display_name":"Ransford Hyman","orcid":null},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ransford Hyman","raw_affiliation_strings":["Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","Dept of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]},{"raw_affiliation_string":"Dept of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027665366","display_name":"N. Ranganathan","orcid":null},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nagarajan Ranganathan","raw_affiliation_strings":["Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","Dept of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]},{"raw_affiliation_string":"Dept of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5098587363","display_name":"Thomas Bingel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Thomas Bingel","raw_affiliation_strings":["East-West Innovation Corporation, Largo, FL, USA","East-West Innovation Corp., Largo, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"East-West Innovation Corporation, Largo, FL, USA","institution_ids":[]},{"raw_affiliation_string":"East-West Innovation Corp., Largo, FL, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047033740","display_name":"Deanne Tran Vo","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Deanne Tran Vo","raw_affiliation_strings":["East-West Innovation Corporation, Largo, FL, USA","East-West Innovation Corp., Largo, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"East-West Innovation Corporation, Largo, FL, USA","institution_ids":[]},{"raw_affiliation_string":"East-West Innovation Corp., Largo, FL, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7187,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.85202527,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"21","issue":"2","first_page":"259","last_page":"269"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5899360179901123},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5483334064483643},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5362799167633057},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.516388475894928},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5019474029541016},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5018513202667236},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4990503787994385},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.44013625383377075},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.43095800280570984},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.427310585975647},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4200568199157715},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2847084701061249},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.27898386120796204},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.26984840631484985},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26467210054397583},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2520885467529297},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.23791536688804626},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.15172168612480164}],"concepts":[{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5899360179901123},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5483334064483643},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5362799167633057},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.516388475894928},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5019474029541016},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5018513202667236},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4990503787994385},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.44013625383377075},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.43095800280570984},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.427310585975647},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4200568199157715},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2847084701061249},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.27898386120796204},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.26984840631484985},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26467210054397583},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2520885467529297},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.23791536688804626},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.15172168612480164},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2012.2186989","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2012.2186989","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":42,"referenced_works":["https://openalex.org/W604599845","https://openalex.org/W1924077319","https://openalex.org/W1971639510","https://openalex.org/W1988123824","https://openalex.org/W1999640823","https://openalex.org/W2004812650","https://openalex.org/W2008689571","https://openalex.org/W2011579672","https://openalex.org/W2039731046","https://openalex.org/W2044963234","https://openalex.org/W2051230585","https://openalex.org/W2068447851","https://openalex.org/W2070316659","https://openalex.org/W2102627413","https://openalex.org/W2103263103","https://openalex.org/W2104253428","https://openalex.org/W2108904252","https://openalex.org/W2110722301","https://openalex.org/W2117378467","https://openalex.org/W2120463846","https://openalex.org/W2123611365","https://openalex.org/W2125095037","https://openalex.org/W2135347849","https://openalex.org/W2144232914","https://openalex.org/W2145458400","https://openalex.org/W2155755017","https://openalex.org/W2156992164","https://openalex.org/W2162705565","https://openalex.org/W2165867688","https://openalex.org/W2168322670","https://openalex.org/W2169281837","https://openalex.org/W2169691372","https://openalex.org/W2210982994","https://openalex.org/W4212875957","https://openalex.org/W4231706861","https://openalex.org/W4238752581","https://openalex.org/W4239807970","https://openalex.org/W4242862917","https://openalex.org/W4256243490","https://openalex.org/W6675992166","https://openalex.org/W6682819323","https://openalex.org/W6684432734"],"related_works":["https://openalex.org/W2159533695","https://openalex.org/W2100329931","https://openalex.org/W4235807419","https://openalex.org/W2145535176","https://openalex.org/W2158805860","https://openalex.org/W4229446324","https://openalex.org/W2117925677","https://openalex.org/W2110367374","https://openalex.org/W2117814846","https://openalex.org/W3140640533"],"abstract_inverted_index":{"Peak":[0],"power":[1,24,28,241,254,301,337],"reduction":[2,21,64,355],"has":[3,228],"been":[4],"a":[5,57,148,162,218],"critical":[6],"challenge":[7],"in":[8,38,65,147,236,258,358],"the":[9,15,27,69,72,84,88,92,99,105,112,116,122,129,139,154,171,174,183,195,207,210,224,229,247,285,312,317,324,328,332,341,345,353,359],"design":[10],"of":[11,22,30,75,83,119,182,221,232,314],"integrated":[12,31],"circuits":[13,290],"impacting":[14],"chip's":[16],"performance":[17],"and":[18,49,90,108,125,157,250,269,281,291,316],"reliability.":[19],"The":[20,141,264],"peak":[23,300],"also":[25,215],"reduces":[26],"density":[29],"circuits.":[32,67],"Due":[33],"to":[34,46,138,145,187,238,245,306,340,352],"large":[35],"IR-voltage":[36],"drops":[37],"circuits,":[39,288],"transistor":[40],"switching":[41,74,200],"slows":[42],"down":[43],"giving":[44],"rise":[45],"timing":[47,185],"violations":[48],"logic":[50],"failures.":[51],"In":[52,68],"this":[53],"paper,":[54],"we":[55],"present":[56],"new":[58],"clock":[59,168,197,208,225,319],"control":[60],"strategy":[61],"for":[62,121,126,323],"peak-power":[63,354],"VLSI":[66],"proposed":[70,175,265,329,333],"method,":[71,344],"simultaneous":[73],"combinational":[76],"paths":[77,89,93,100,142],"is":[78,214,267],"minimized":[79],"by":[80,327],"taking":[81],"advantage":[82,181],"delay":[85],"slacks":[86],"among":[87],"clustering":[91,113],"with":[94,277],"similar":[95],"slack":[96,110,155,186],"values.":[97],"Once":[98],"are":[101,143,202],"identified":[102,320],"based":[103,152],"on":[104,153,166,170,284,311],"path":[106],"delays":[107],"their":[109],"values,":[111],"algorithm":[114],"determines":[115],"ideal":[117],"number":[118,313],"clusters":[120,146,315],"given":[123,325],"circuit":[124,189,326],"each":[127,158],"cluster":[128,159],"maximum":[130],"possible":[131,165],"phase":[132,163],"shift":[133,164],"that":[134,299],"can":[135,302,347],"be":[136,303,348],"applied":[137],"clock.":[140],"assigned":[144],"load":[149],"balanced":[150],"manner":[151],"values":[156],"will":[160],"have":[161],"its":[167],"depending":[169,310],"slack.":[172],"Thus,":[173],"register-transfer":[176],"level":[177],"(RTL)":[178],"method":[179,266,334],"takes":[180],"logic-path":[184],"re-schedule":[188],"activities":[190,201],"at":[191,307],"optimal":[192],"intervals":[193],"within":[194,223],"unaltered":[196],"period.":[198,226],"When":[199],"redistributed":[203],"more":[204],"evenly":[205],"across":[206,217],"period,":[209],"IC":[211],"supply-current":[212],"consumption":[213],"spread":[216],"wider":[219],"range":[220],"time":[222],"This":[227],"beneficial":[230],"effect":[231],"reducing":[233,239],"peak-current":[234],"draw":[235,242],"addition":[237],"RMS":[240],"without":[243,251],"having":[244],"change":[246],"operating":[248],"frequency":[249],"utilizing":[252],"additional":[253],"supply":[255],"voltages":[256],"as":[257,321,356],"dual":[259],"or":[260],"multi":[261],"VT":[262],"approaches.":[263],"implemented":[268],"tested":[270],"through":[271],"simulations":[272],"using":[273],"an":[274],"experimental":[275,360],"setup":[276],"Synopsys":[278],"Tools":[279,283],"Suite":[280],"Cadence":[282],"ISCAS'85":[286],"benchmark":[287],"OpenCore":[289],"LEON":[292],"processor":[293],"multiplier":[294],"circuit.":[295],"Experimental":[296],"results":[297,361],"indicate":[298],"reduced":[304],"significantly":[305],"least":[308],"72%":[309],"phase-shifted":[318],"suitable":[322],"algorithms.":[330],"Although":[331],"incurs":[335],"some":[336],"overhead":[338,346],"compared":[339,351],"traditional":[342],"clocking":[343],"made":[349],"negligible":[350],"seen":[357],"presented.":[362]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}