{"id":"https://openalex.org/W1998492944","doi":"https://doi.org/10.1109/tvlsi.2011.2180548","title":"Formal Verification of Architectural Power Intent","display_name":"Formal Verification of Architectural Power Intent","publication_year":2012,"publication_date":"2012-01-17","ids":{"openalex":"https://openalex.org/W1998492944","doi":"https://doi.org/10.1109/tvlsi.2011.2180548","mag":"1998492944"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2180548","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2180548","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022880201","display_name":"Aritra Hazra","orcid":"https://orcid.org/0000-0003-2076-3577"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aritra Hazra","raw_affiliation_strings":["Indian Institute of Technology, Kharagpur, West Bengal, India","Indian Institute of Technology Kharagpur, Kharagpur, India;"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Kharagpur, West Bengal, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, Kharagpur, India;","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086904282","display_name":"Sahil Goyal","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sahil Goyal","raw_affiliation_strings":["Barclays Capital, Singapore","Barclays Capital, Singapore, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Barclays Capital, Singapore","institution_ids":[]},{"raw_affiliation_string":"Barclays Capital, Singapore, Singapore","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033329960","display_name":"Pallab Dasgupta","orcid":"https://orcid.org/0000-0002-2178-8154"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pallab Dasgupta","raw_affiliation_strings":["Indian Institute of Technology, Kharagpur, West Bengal, India","Indian Institute of Technology Kharagpur, Kharagpur, India;"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Kharagpur, West Bengal, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, Kharagpur, India;","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102172297","display_name":"Ajit Pal","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ajit Pal","raw_affiliation_strings":["Indian Institute of Technology, Kharagpur, West Bengal, India","Indian Institute of Technology Kharagpur, Kharagpur, India;"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Kharagpur, West Bengal, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, Kharagpur, India;","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7489,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.85494235,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"21","issue":"1","first_page":"78","last_page":"91"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7241063714027405},{"id":"https://openalex.org/keywords/power-domains","display_name":"Power domains","score":0.6930442452430725},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.5478063821792603},{"id":"https://openalex.org/keywords/novelty","display_name":"Novelty","score":0.4794125258922577},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.46741223335266113},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4485085904598236},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4381732940673828},{"id":"https://openalex.org/keywords/bridge","display_name":"Bridge (graph theory)","score":0.43816107511520386},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4022792875766754},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3706858158111572},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3554813861846924},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.34009361267089844},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0897858738899231}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7241063714027405},{"id":"https://openalex.org/C16021271","wikidata":"https://www.wikidata.org/wiki/Q17152552","display_name":"Power domains","level":3,"score":0.6930442452430725},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.5478063821792603},{"id":"https://openalex.org/C2778738651","wikidata":"https://www.wikidata.org/wiki/Q16546687","display_name":"Novelty","level":2,"score":0.4794125258922577},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.46741223335266113},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4485085904598236},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4381732940673828},{"id":"https://openalex.org/C100776233","wikidata":"https://www.wikidata.org/wiki/Q2532492","display_name":"Bridge (graph theory)","level":2,"score":0.43816107511520386},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4022792875766754},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3706858158111572},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3554813861846924},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.34009361267089844},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0897858738899231},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C126322002","wikidata":"https://www.wikidata.org/wiki/Q11180","display_name":"Internal medicine","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C27206212","wikidata":"https://www.wikidata.org/wiki/Q34178","display_name":"Theology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2180548","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2180548","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1543643719","https://openalex.org/W1827563491","https://openalex.org/W1869164539","https://openalex.org/W2070015279","https://openalex.org/W2117299787","https://openalex.org/W2129109920","https://openalex.org/W2139542266","https://openalex.org/W2139942673","https://openalex.org/W2141649130","https://openalex.org/W2151494804","https://openalex.org/W2158899676","https://openalex.org/W2162211138","https://openalex.org/W2485157670","https://openalex.org/W3145549963","https://openalex.org/W3147062543","https://openalex.org/W6638479603","https://openalex.org/W6679454873"],"related_works":["https://openalex.org/W2381242807","https://openalex.org/W3126131230","https://openalex.org/W2347541121","https://openalex.org/W4288804799","https://openalex.org/W2080951048","https://openalex.org/W3089617106","https://openalex.org/W3032237421","https://openalex.org/W2390346111","https://openalex.org/W3011883280","https://openalex.org/W2112298791"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,92,119],"verification":[4],"framework":[5,40],"that":[6,44,72],"attempts":[7],"to":[8,79,135],"bridge":[9],"the":[10,16,22,25,38,45,73,82,113,125,137,140],"disconnect":[11],"between":[12],"high-level":[13,52],"properties":[14,49,59,75],"capturing":[15],"architectural":[17,46],"power":[18,26,47,69,85],"management":[19,27,86],"strategy":[20],"and":[21,71,98,128],"implementation":[23],"of":[24,37,68,95,109,132,139],"control":[28,33,62,115],"logic":[29],"using":[30,51],"low-level":[31,61,114],"per-domain":[32],"signals.":[34],"The":[35,88],"novelty":[36],"proposed":[39,89,126,141],"is":[41,99],"in":[42],"demonstrating":[43],"intent":[48],"developed":[50],"artifacts":[53],"can":[54,76],"be":[55,77],"automatically":[56],"translated":[57],"into":[58],"over":[60],"sequences":[63],"gleaned":[64],"from":[65],"UPF":[66],"specifications":[67],"domains,":[70],"resulting":[74],"used":[78],"formally":[80],"verify":[81],"global":[83],"on-chip":[84],"logic.":[87],"translation":[90],"uses":[91],"considerable":[93],"amount":[94],"domain":[96],"knowledge":[97],"also":[100],"not":[101],"purely":[102],"syntactic,":[103],"because":[104],"it":[105],"requires":[106],"formal":[107],"extraction":[108],"timing":[110],"information":[111],"for":[112],"sequences.":[116],"We":[117],"present":[118],"tool,":[120],"called":[121],"POWER-TRUCTOR":[122],"which":[123],"enables":[124],"framework,":[127],"several":[129],"test":[130],"cases":[131],"significant":[133],"complexity":[134],"demonstrate":[136],"feasibility":[138],"framework.":[142]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":4}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}