{"id":"https://openalex.org/W1991075467","doi":"https://doi.org/10.1109/tvlsi.2011.2178046","title":"Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits","display_name":"Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits","publication_year":2011,"publication_date":"2011-12-29","ids":{"openalex":"https://openalex.org/W1991075467","doi":"https://doi.org/10.1109/tvlsi.2011.2178046","mag":"1991075467"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2178046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2178046","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063929219","display_name":"Hassan Mostafa","orcid":"https://orcid.org/0000-0003-0043-5007"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Hassan Mostafa","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112829693","display_name":"Mohab Anis","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mohab Anis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111829312","display_name":"M.I. Elmasry","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mohamed Elmasry","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2703,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.59766589,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"21","issue":"1","first_page":"92","last_page":"101"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9394124150276184},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.6952681541442871},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6663100123405457},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.6386997103691101},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5304179787635803},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5205087065696716},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5074908137321472},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4664890766143799},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.4633977711200714},{"id":"https://openalex.org/keywords/parasitic-capacitance","display_name":"Parasitic capacitance","score":0.4541047513484955},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4431438148021698},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41653311252593994},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38425353169441223},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3631761074066162},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2656625509262085},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2582879960536957},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.22102755308151245},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07604971528053284}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9394124150276184},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.6952681541442871},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6663100123405457},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.6386997103691101},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5304179787635803},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5205087065696716},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5074908137321472},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4664890766143799},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.4633977711200714},{"id":"https://openalex.org/C154318817","wikidata":"https://www.wikidata.org/wiki/Q2157249","display_name":"Parasitic capacitance","level":4,"score":0.4541047513484955},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4431438148021698},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41653311252593994},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38425353169441223},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3631761074066162},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2656625509262085},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2582879960536957},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.22102755308151245},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07604971528053284},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C147789679","wikidata":"https://www.wikidata.org/wiki/Q11372","display_name":"Physical chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2178046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2178046","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W612784192","https://openalex.org/W1505220924","https://openalex.org/W1597620877","https://openalex.org/W1661368752","https://openalex.org/W2005625397","https://openalex.org/W2006589289","https://openalex.org/W2033443176","https://openalex.org/W2045074698","https://openalex.org/W2076691152","https://openalex.org/W2099320289","https://openalex.org/W2110103617","https://openalex.org/W2111702626","https://openalex.org/W2112723377","https://openalex.org/W2114810610","https://openalex.org/W2116359224","https://openalex.org/W2116597081","https://openalex.org/W2117475675","https://openalex.org/W2117648153","https://openalex.org/W2119591281","https://openalex.org/W2123009614","https://openalex.org/W2126051429","https://openalex.org/W2131581217","https://openalex.org/W2132621842","https://openalex.org/W2134067926","https://openalex.org/W2140823559","https://openalex.org/W2149855589","https://openalex.org/W2154477062","https://openalex.org/W2155583994","https://openalex.org/W2161648718","https://openalex.org/W2171922263","https://openalex.org/W2949464251","https://openalex.org/W3146563601","https://openalex.org/W6630193252"],"related_works":["https://openalex.org/W2119312496","https://openalex.org/W4247460323","https://openalex.org/W2537086382","https://openalex.org/W2136045454","https://openalex.org/W2118528827","https://openalex.org/W2153162275","https://openalex.org/W2107909712","https://openalex.org/W2775062502","https://openalex.org/W1521345290","https://openalex.org/W3176114933"],"abstract_inverted_index":{"SRAM":[0,36,44,103,141],"has":[1],"become":[2],"the":[3,15,32,43,51,56,75,96,102,112,131,134,148],"dominant":[4],"block":[5],"in":[6],"modern":[7],"ICs":[8],"and":[9,49,78],"constitutes":[10],"more":[11],"than":[12],"50%":[13],"of":[14,20,31,133,146],"die":[16],"area.":[17],"The":[18],"increase":[19,41],"process":[21,39,108],"variations":[22,40,109],"with":[23],"continued":[24],"CMOS":[25,127],"technology":[26],"scaling":[27],"is":[28,71,144],"considered":[29],"one":[30],"major":[33],"challenges":[34],"for":[35,95],"designers.":[37],"This":[38],"causes":[42],"cells":[45,142],"to":[46,99,121,138,154],"functionally":[47],"fail":[48],"reduces":[50],"chip":[52],"functional":[53],"yield":[54,106,151],"considering":[55],"static":[57],"noise":[58],"margin":[59],"stability":[60],"failures":[61,68,81],"(i.e.,":[62,69,82],"cell":[63,70],"flips":[64],"when":[65],"accessed),":[66],"write":[67,76],"not":[72],"written":[73],"within":[74],"window),":[77],"read":[79,84,104,149],"access":[80,105,150],"incorrect":[83],"operation).":[85],"In":[86],"this":[87],"paper,":[88],"novel":[89],"negative":[90,135],"capacitance":[91,136],"circuits":[92],"are":[93],"developed,":[94],"first":[97],"time,":[98],"statistically":[100],"improve":[101],"under":[107],"by":[110],"reducing":[111],"bitlines":[113],"parasitic":[114],"capacitance.":[115],"Post":[116],"layout":[117],"simulation":[118],"results,":[119],"referring":[120],"an":[122],"industrial":[123],"hardware-calibrated":[124],"TSMC":[125],"65-nm":[126],"technology,":[128],"show":[129],"that":[130],"adoption":[132],"circuit":[137],"a":[139],"512":[140],"column":[143],"capable":[145],"improving":[147],"from":[152],"61.9%":[153],"100%.":[155]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}