{"id":"https://openalex.org/W2013445609","doi":"https://doi.org/10.1109/tvlsi.2011.2173361","title":"A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction","display_name":"A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction","publication_year":2011,"publication_date":"2011-11-28","ids":{"openalex":"https://openalex.org/W2013445609","doi":"https://doi.org/10.1109/tvlsi.2011.2173361","mag":"2013445609"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2173361","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2173361","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033997592","display_name":"Fu-Wei Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Fu-Wei Chen","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001360499","display_name":"Shih-Liang Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I173632517","display_name":"MediaTek (China)","ror":"https://ror.org/05xvgy636","country_code":"CN","type":"company","lineage":["https://openalex.org/I173632517","https://openalex.org/I4210148979"]},{"id":"https://openalex.org/I4210148979","display_name":"MediaTek (Taiwan)","ror":"https://ror.org/05g9jck81","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210148979"]}],"countries":["CN","TW"],"is_corresponding":false,"raw_author_name":"Shih-Liang Chen","raw_affiliation_strings":["MediaTek Corporation Limited, Hsinchu, Taiwan",", Mediatek Inc., Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MediaTek Corporation Limited, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148979"]},{"raw_affiliation_string":", Mediatek Inc., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I173632517"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014342696","display_name":"Yung\u2010Sheng Lin","orcid":"https://orcid.org/0000-0002-9522-1812"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Sheng Lin","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan","Taiwan Semicond. Manuf. Co. Ltd., Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]},{"raw_affiliation_string":"Taiwan Semicond. Manuf. Co. Ltd., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043578401","display_name":"TingTing Hwang","orcid":"https://orcid.org/0000-0002-7206-560X"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"TingTing Hwang","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.09102045,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"20","issue":"12","first_page":"2255","last_page":"2264"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.8781867027282715},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.709985613822937},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5905470252037048},{"id":"https://openalex.org/keywords/drop","display_name":"Drop (telecommunication)","score":0.5644780993461609},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.48628318309783936},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47832489013671875},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4680594801902771},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4585011899471283},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.44687703251838684},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41386622190475464},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3693666160106659},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3231501877307892},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.29313451051712036},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27456390857696533},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26197558641433716},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.21920838952064514},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2038339376449585}],"concepts":[{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.8781867027282715},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.709985613822937},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5905470252037048},{"id":"https://openalex.org/C2781345722","wikidata":"https://www.wikidata.org/wiki/Q5308388","display_name":"Drop (telecommunication)","level":2,"score":0.5644780993461609},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.48628318309783936},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47832489013671875},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4680594801902771},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4585011899471283},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.44687703251838684},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41386622190475464},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3693666160106659},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3231501877307892},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.29313451051712036},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27456390857696533},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26197558641433716},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.21920838952064514},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2038339376449585},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2173361","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2173361","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W156271197","https://openalex.org/W1568407911","https://openalex.org/W1849928240","https://openalex.org/W1915857416","https://openalex.org/W2056864235","https://openalex.org/W2064139224","https://openalex.org/W2100925694","https://openalex.org/W2111962400","https://openalex.org/W2125014350","https://openalex.org/W2126872604","https://openalex.org/W2130785299","https://openalex.org/W2132565185","https://openalex.org/W2171709869","https://openalex.org/W3146045665","https://openalex.org/W4240059611","https://openalex.org/W4242107829","https://openalex.org/W6678356202","https://openalex.org/W6678897769","https://openalex.org/W6823815530"],"related_works":["https://openalex.org/W4285708951","https://openalex.org/W2786111245","https://openalex.org/W1979305473","https://openalex.org/W3009953521","https://openalex.org/W4234763172","https://openalex.org/W2125317684","https://openalex.org/W2992024382","https://openalex.org/W1588361197","https://openalex.org/W2147986372","https://openalex.org/W2258554167"],"abstract_inverted_index":{"To":[0],"guarantee":[1],"that":[2,44,102,126],"an":[3,16,130],"application-specific":[4],"integrated":[5],"circuit":[6],"(ASIC)":[7],"meets":[8],"its":[9],"timing":[10],"requirement,":[11],"at-speed":[12,26,73],"scan":[13,27],"testing":[14],"becomes":[15],"indispensable":[17],"procedure":[18],"for":[19],"verifying":[20],"the":[21,30,35,48,63,76,82,85,103,120],"performance":[22],"of":[23,78,87,132,136],"ASIC.":[24],"However,":[25,75],"test":[28,38,151],"suffers":[29],"test-induced":[31],"yield":[32],"loss.":[33],"Because":[34],"switching-activity":[36,105],"in":[37,45,149],"mode":[39],"is":[40,62,106],"much":[41],"higher":[42],"than":[43],"normal":[46],"mode,":[47],"switching-induced":[49],"large":[50],"current":[51],"drawn":[52],"causes":[53],"severe":[54],"IR":[55],"drop":[56],"and":[57,84,119],"increases":[58],"gate":[59],"delay.":[60],"X-filling":[61,79],"most":[64],"commonly":[65],"used":[66],"technique":[67],"to":[68,108,141],"reduce":[69],"IR-drop":[70,115,138],"effect":[71],"during":[72],"test.":[74],"effectiveness":[77],"depends":[80],"on":[81,123],"number":[83],"characteristic":[86],"X-bit":[88],"distribution.":[89],"In":[90],"this":[91],"paper,":[92],"we":[93],"propose":[94],"a":[95,142],"physical-location-aware":[96],"X-identification":[97],"which":[98,145],"redistributes":[99,146],"X-bits":[100,147],"so":[101],"maximum":[104,137],"guaranteed":[107],"be":[109],"reduced":[110],"after":[111],"X-filling.":[112],"We":[113],"estimate":[114],"using":[116],"RedHawk":[117],"tool":[118],"experimental":[121],"results":[122],"ITC'99":[124],"show":[125],"our":[127],"method":[128],"has":[129],"average":[131],"9.42%":[133],"more":[134],"reduction":[135],"as":[139],"compared":[140],"previous":[143],"work":[144],"evenly":[148],"all":[150],"vectors.":[152]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}