{"id":"https://openalex.org/W2049281288","doi":"https://doi.org/10.1109/tvlsi.2011.2169094","title":"Direct Compare of Information Coded With Error-Correcting Codes","display_name":"Direct Compare of Information Coded With Error-Correcting Codes","publication_year":2011,"publication_date":"2011-10-17","ids":{"openalex":"https://openalex.org/W2049281288","doi":"https://doi.org/10.1109/tvlsi.2011.2169094","mag":"2049281288"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2169094","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2169094","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031436726","display_name":"Wei Wu","orcid":"https://orcid.org/0000-0003-0401-7363"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Wei Wu","raw_affiliation_strings":["Circuit and System Research, Intel Labs, Hillsboro, OR","Circuit & Syst. Res., Intel Labs., Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Circuit and System Research, Intel Labs, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuit & Syst. Res., Intel Labs., Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006467285","display_name":"Dinesh Somasekhar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dinesh Somasekhar","raw_affiliation_strings":["Intel Labs, Hillsboro, OR","[Intel Labs, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Intel Labs, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel Labs, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113824454","display_name":"Shih\u2010Lien Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shih-Lien Lu","raw_affiliation_strings":["Circuit and System Research, Intel Labs, Hillsboro, OR","Circuit & Syst. Res., Intel Labs., Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Circuit and System Research, Intel Labs, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuit & Syst. Res., Intel Labs., Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5031436726"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.24167956,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.55511514,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"20","issue":"11","first_page":"2147","last_page":"2151"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.836461067199707},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6972541213035583},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.5907111763954163},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5848608016967773},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5009005069732666},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.45774927735328674},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4113156795501709},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39559218287467957},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38723063468933105},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35779210925102234}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.836461067199707},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6972541213035583},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.5907111763954163},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5848608016967773},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5009005069732666},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.45774927735328674},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4113156795501709},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39559218287467957},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38723063468933105},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35779210925102234},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2169094","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2169094","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1533071485","https://openalex.org/W1691434136","https://openalex.org/W2014409146","https://openalex.org/W2077874318","https://openalex.org/W2124438715","https://openalex.org/W2130646500","https://openalex.org/W2293347572","https://openalex.org/W4234365927"],"related_works":["https://openalex.org/W3203142394","https://openalex.org/W4302615923","https://openalex.org/W1974101135","https://openalex.org/W2351061015","https://openalex.org/W2017509870","https://openalex.org/W2980068837","https://openalex.org/W2098872742","https://openalex.org/W2394408226","https://openalex.org/W4389168214","https://openalex.org/W4366457933"],"abstract_inverted_index":{"There":[0],"are":[1,125],"situations":[2],"in":[3],"a":[4,15,91],"computing":[5],"system":[6],"where":[7],"incoming":[8,70],"information":[9,99],"needs":[10],"to":[11,20,52,66,93],"be":[12],"compared":[13],"with":[14,41,68,101],"piece":[16],"of":[17],"stored":[18,37,55],"data":[19,38],"locate":[21],"the":[22,36,48,54,69,78,95,105],"matching":[23],"entry,":[24],"e.g.,":[25],"cache":[26,106],"tag":[27,107],"array":[28,108],"lookup":[29],"and":[30,58,74,113,121],"translation":[31],"look-aside":[32],"buffer":[33],"matching.":[34],"If":[35],"is":[39,51,64,83],"protected":[40],"error-correcting":[42],"codes":[43],"(ECC)":[44],"for":[45,98],"reliability":[46],"reason,":[47],"previous":[49],"solution":[50],"access":[53,80],"information,":[56],"decode":[57],"correct":[59],"if":[60],"necessary":[61],"before":[62],"it":[63],"used":[65],"compare":[67,96],"data.":[71],"The":[72],"decoding":[73],"correcting":[75],"step":[76],"increases":[77],"total":[79],"time,":[81],"which":[82],"often":[84],"critical.":[85],"In":[86],"this":[87],"paper,":[88],"we":[89],"propose":[90],"method":[92],"improve":[94],"latency":[97,123],"encoded":[100],"ECC.":[102],"We":[103],"use":[104],"look-up":[109],"as":[110],"an":[111],"example,":[112],"results":[114],"show":[115],"that":[116],"30%":[117],"gate":[118],"count":[119],"reduction":[120,124],"12%":[122],"achieved.":[126]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
