{"id":"https://openalex.org/W2087908752","doi":"https://doi.org/10.1109/tvlsi.2011.2166416","title":"Formal-Analysis-Based Trace Computation for Post-Silicon Debug","display_name":"Formal-Analysis-Based Trace Computation for Post-Silicon Debug","publication_year":2011,"publication_date":"2011-10-12","ids":{"openalex":"https://openalex.org/W2087908752","doi":"https://doi.org/10.1109/tvlsi.2011.2166416","mag":"2087908752"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2166416","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2166416","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089383052","display_name":"Marcel Gort","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Marcel Gort","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada#TAB#","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111424365","display_name":"Flavio M. De Paula","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Flavio M. De Paula","raw_affiliation_strings":["Department of Computer Science, University of British Columbia, Vancouver, BC, Canada","Department of Computer Science, University of British Columbia, Vancouver, BC Canada"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Department of Computer Science, University of British Columbia, Vancouver, BC Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019134730","display_name":"Johnny J.W. Kuan","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Johnny J. W. Kuan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026788167","display_name":"Tor M. Aamodt","orcid":"https://orcid.org/0000-0003-1161-692X"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Tor M. Aamodt","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050411743","display_name":"Alan J. Hu","orcid":"https://orcid.org/0000-0002-4276-0169"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Alan J. Hu","raw_affiliation_strings":["Department of Computer Science, University of British Columbia, Vancouver, BC, Canada","Department of Computer Science, University of British Columbia, Vancouver, BC Canada"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Department of Computer Science, University of British Columbia, Vancouver, BC Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J. E. Wilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052037169","display_name":"Jin Yang","orcid":"https://orcid.org/0000-0002-4372-926X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jin Yang","raw_affiliation_strings":["Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR, USA","[CAD Labs, Intel Corporation, Hillsboro, OR, USA]"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[CAD Labs, Intel Corporation, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5089383052"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.2519,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.56428367,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"20","issue":"11","first_page":"1997","last_page":"2010"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7432550191879272},{"id":"https://openalex.org/keywords/trace","display_name":"TRACE (psycholinguistics)","score":0.6059898734092712},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6023939847946167},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5592270493507385},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.46954283118247986},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4044686257839203},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36895817518234253},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35651078820228577},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19482606649398804},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.16636544466018677},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.1304706335067749}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7432550191879272},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.6059898734092712},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6023939847946167},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5592270493507385},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.46954283118247986},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4044686257839203},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36895817518234253},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35651078820228577},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19482606649398804},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.16636544466018677},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.1304706335067749},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2166416","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2166416","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320310709","display_name":"CMC Microsystems","ror":"https://ror.org/03k70ea39"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W193562070","https://openalex.org/W1917409762","https://openalex.org/W2004831359","https://openalex.org/W2088256110","https://openalex.org/W2088391469","https://openalex.org/W2120263045","https://openalex.org/W2121316343","https://openalex.org/W2122146819","https://openalex.org/W2123198997","https://openalex.org/W2123205813","https://openalex.org/W2129323560","https://openalex.org/W2129745413","https://openalex.org/W2132721535","https://openalex.org/W2132894060","https://openalex.org/W2140980952","https://openalex.org/W2141261568","https://openalex.org/W2143388350","https://openalex.org/W2145314233","https://openalex.org/W2159004509","https://openalex.org/W2159381165","https://openalex.org/W2166930733","https://openalex.org/W2168098726","https://openalex.org/W3139542001","https://openalex.org/W3141991053","https://openalex.org/W4230169210","https://openalex.org/W6607997357"],"related_works":["https://openalex.org/W1483845062","https://openalex.org/W2390095984","https://openalex.org/W1919905746","https://openalex.org/W2115737686","https://openalex.org/W2162923618","https://openalex.org/W3130559624","https://openalex.org/W1572523360","https://openalex.org/W1964713618","https://openalex.org/W2156120365","https://openalex.org/W2290768160"],"abstract_inverted_index":{"This":[0,54],"paper":[1],"presents":[2],"a":[3,9,15,18,23,58,86,102],"post-silicon":[4],"debug":[5,37,98],"methodology":[6,118],"that":[7,41],"provides":[8],"means":[10],"to":[11,70,101],"rewind,":[12],"or":[13],"backspace,":[14],"chip":[16],"from":[17],"known":[19],"crash":[20],"state":[21,74],"using":[22,85,116],"combination":[24],"of":[25,75,91,111],"on-chip":[26,48],"real-time":[27],"data":[28],"collection":[29],"and":[30,50,80],"off-chip":[31],"formal":[32,106],"analysis":[33],"methods.":[34],"A":[35],"complete":[36],"flow":[38,79],"is":[39],"presented":[40,119],"considers":[42],"practical":[43],"considerations":[44],"such":[45],"as":[46],"area,":[47],"non-determinism":[49],"signal":[51],"propagation":[52],"delay.":[53],"flow,":[55],"along":[56],"with":[57,96],"low-overhead":[59],"breakpoint":[60],"circuit,":[61],"allows":[62],"for":[63],"state-accurate":[64],"breakpointing":[65],"capabilities":[66],"without":[67],"the":[68,72,76,97,105,117],"need":[69],"monitor":[71],"entire":[73],"chip.":[77],"The":[78],"associated":[81],"hardware":[82,87,99],"was":[83],"tested":[84],"prototype,":[88],"which":[89],"consists":[90],"an":[92],"OpenRISC":[93],"processor":[94],"instrumented":[95],"connected":[100],"PC":[103],"running":[104],"verification":[107],"algorithms.":[108],"Traces":[109],"hundreds":[110],"cycles":[112],"long":[113],"were":[114],"obtained":[115],"in":[120],"this":[121],"paper.":[122]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
