{"id":"https://openalex.org/W2018356883","doi":"https://doi.org/10.1109/tvlsi.2011.2161786","title":"Generation of Mixed Test Sets for Transition Faults","display_name":"Generation of Mixed Test Sets for Transition Faults","publication_year":2011,"publication_date":"2011-08-15","ids":{"openalex":"https://openalex.org/W2018356883","doi":"https://doi.org/10.1109/tvlsi.2011.2161786","mag":"2018356883"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2161786","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2161786","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070677022","display_name":"Irith Pomeranz","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Irith Pomeranz","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","School of Electrical and Computer Engineering, Purdue University, West-Lafayette, IN#TAB#"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West-Lafayette, IN#TAB#","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5070677022"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":1.763,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.85138876,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"20","issue":"10","first_page":"1895","last_page":"1899"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9902999997138977,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47182780504226685},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.46747517585754395},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4231386184692383},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.36448925733566284},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12961536645889282}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47182780504226685},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.46747517585754395},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4231386184692383},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.36448925733566284},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12961536645889282}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2161786","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2161786","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1863819993","https://openalex.org/W2024588581","https://openalex.org/W2096146619","https://openalex.org/W2101278273","https://openalex.org/W2102127226","https://openalex.org/W2118744758","https://openalex.org/W2131041854","https://openalex.org/W2134998505","https://openalex.org/W2144898259","https://openalex.org/W2149124583","https://openalex.org/W2157726388"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2051487156","https://openalex.org/W2073681303","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2382290278","https://openalex.org/W2478288626","https://openalex.org/W4391913857"],"abstract_inverted_index":{"Test":[0],"sets":[1],"that":[2,85,102],"contain":[3],"both":[4,87],"broadside":[5,88,113],"and":[6,55,62,67,89],"skewed-load":[7,90,110],"tests":[8,25],"are":[9,60,72],"important":[10],"for":[11,19,106,134,149],"achieving":[12],"the":[13,78,145,152],"highest":[14],"possible":[15],"delay":[16],"fault":[17],"coverage":[18],"standard-scan":[20],"circuits.":[21],"Both":[22],"types":[23,148],"of":[24,80,144,151],"can":[26,103],"be":[27,104],"represented":[28],"as":[29],"\u3008s":[30],"<sub":[31,36,41,46,52,57,64,69,97,122],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[32,37,42,47,53,58,65,70,98,123],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">1</sub>":[33,38,54,66],",":[34,39,44],"v":[35,45,63,68],"s":[40,51,56,96,121],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sub>":[43,48,59,71,99,124],"\u3009,":[49],"where":[50],"states,":[61],"primary":[73],"input":[74],"vectors.":[75],"To":[76],"facilitate":[77],"generation":[79,138],"a":[81,100,109,112,136],"mixed":[82],"test":[83,114,137,147],"set":[84],"contains":[86],"tests,":[91],"this":[92,132],"paper":[93,130],"associates":[94],"with":[95,120],"property":[101,133],"used":[105],"estimating":[107],"whether":[108],"or":[111],"is":[115],"more":[116],"likely":[117],"to":[118,140],"exist":[119],"in":[125],"its":[126],"second":[127],"pattern.":[128],"This":[129],"uses":[131],"guiding":[135],"procedure":[139],"consider":[141],"only":[142],"one":[143],"two":[146],"most":[150],"target":[153],"faults.":[154]},"counts_by_year":[{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}