{"id":"https://openalex.org/W1986285024","doi":"https://doi.org/10.1109/tvlsi.2011.2160747","title":"Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration","display_name":"Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration","publication_year":2011,"publication_date":"2011-08-15","ids":{"openalex":"https://openalex.org/W1986285024","doi":"https://doi.org/10.1109/tvlsi.2011.2160747","mag":"1986285024"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2160747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2160747","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053635255","display_name":"Guiqiang Dong","orcid":null},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Guiqiang Dong","raw_affiliation_strings":["Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY, USA","Electr., Comput. & Syst. Eng. Dept., Rensselaer Polytech. Inst. (RPI), Troy, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]},{"raw_affiliation_string":"Electr., Comput. & Syst. Eng. Dept., Rensselaer Polytech. Inst. (RPI), Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065412990","display_name":"Yangyang Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yangyang Pan","raw_affiliation_strings":["Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY, USA","Electr., Comput. & Syst. Eng. Dept., Rensselaer Polytech. Inst. (RPI), Troy, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]},{"raw_affiliation_string":"Electr., Comput. & Syst. Eng. Dept., Rensselaer Polytech. Inst. (RPI), Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081778811","display_name":"Ningde Xie","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ningde Xie","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005498232","display_name":"C. Varanasi","orcid":null},"institutions":[{"id":"https://openalex.org/I11912373","display_name":"Micron (United States)","ror":"https://ror.org/02fv52296","country_code":"US","type":"company","lineage":["https://openalex.org/I11912373"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chandra Varanasi","raw_affiliation_strings":["Micron Technology, San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Micron Technology, San Jose, CA, USA","institution_ids":["https://openalex.org/I11912373"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100378782","display_name":"Tong Zhang","orcid":"https://orcid.org/0000-0002-3481-6062"},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tong Zhang","raw_affiliation_strings":["Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY, USA","Electr., Comput. & Syst. Eng. Dept., Rensselaer Polytech. Inst. (RPI), Troy, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]},{"raw_affiliation_string":"Electr., Comput. & Syst. Eng. Dept., Rensselaer Polytech. Inst. (RPI), Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":7.1552,"has_fulltext":false,"cited_by_count":65,"citation_normalized_percentile":{"value":0.97132791,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"20","issue":"9","first_page":"1705","last_page":"1714"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7154431939125061},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.70756596326828},{"id":"https://openalex.org/keywords/flash-file-system","display_name":"Flash file system","score":0.6590893268585205},{"id":"https://openalex.org/keywords/computer-data-storage","display_name":"Computer data storage","score":0.5894045829772949},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.5537763237953186},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.4855058193206787},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.47138673067092896},{"id":"https://openalex.org/keywords/bch-code","display_name":"BCH code","score":0.4574737548828125},{"id":"https://openalex.org/keywords/erasure-code","display_name":"Erasure code","score":0.44315701723098755},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.43861353397369385},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.41126328706741333},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40206512808799744},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39518454670906067},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.3555786609649658},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3382483124732971},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3223024606704712},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.21766340732574463},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.21165144443511963},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.17221209406852722},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16259989142417908},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1082783043384552}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7154431939125061},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.70756596326828},{"id":"https://openalex.org/C27670709","wikidata":"https://www.wikidata.org/wiki/Q5457555","display_name":"Flash file system","level":4,"score":0.6590893268585205},{"id":"https://openalex.org/C194739806","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Computer data storage","level":2,"score":0.5894045829772949},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.5537763237953186},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.4855058193206787},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.47138673067092896},{"id":"https://openalex.org/C42276685","wikidata":"https://www.wikidata.org/wiki/Q795705","display_name":"BCH code","level":3,"score":0.4574737548828125},{"id":"https://openalex.org/C137529215","wikidata":"https://www.wikidata.org/wiki/Q5385031","display_name":"Erasure code","level":3,"score":0.44315701723098755},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.43861353397369385},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.41126328706741333},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40206512808799744},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39518454670906067},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.3555786609649658},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3382483124732971},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3223024606704712},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.21766340732574463},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.21165144443511963},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.17221209406852722},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16259989142417908},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1082783043384552},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2160747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2160747","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W187677220","https://openalex.org/W1651818244","https://openalex.org/W1972127875","https://openalex.org/W1994828974","https://openalex.org/W2002129922","https://openalex.org/W2017159197","https://openalex.org/W2035604011","https://openalex.org/W2061539348","https://openalex.org/W2072766183","https://openalex.org/W2098731682","https://openalex.org/W2099111195","https://openalex.org/W2099153499","https://openalex.org/W2102646391","https://openalex.org/W2102837996","https://openalex.org/W2106673654","https://openalex.org/W2109136771","https://openalex.org/W2109987538","https://openalex.org/W2110395205","https://openalex.org/W2111087997","https://openalex.org/W2114512042","https://openalex.org/W2123798696","https://openalex.org/W2135210684","https://openalex.org/W2135288278","https://openalex.org/W2135856210","https://openalex.org/W2149453042","https://openalex.org/W2164177293","https://openalex.org/W2169032695","https://openalex.org/W2171507277","https://openalex.org/W2535010479","https://openalex.org/W6675131915","https://openalex.org/W6675635200"],"related_works":["https://openalex.org/W2386754275","https://openalex.org/W2375456104","https://openalex.org/W2022090292","https://openalex.org/W2348516269","https://openalex.org/W3027170713","https://openalex.org/W2024198870","https://openalex.org/W2427787916","https://openalex.org/W2370381489","https://openalex.org/W2348980775","https://openalex.org/W2054973977"],"abstract_inverted_index":{"Today":[0],"and":[1,34,124,159,201],"future":[2],"NAND":[3,112,196,214],"flash":[4,113,197,215],"memory":[5,114,187,198],"will":[6],"heavily":[7],"rely":[8],"on":[9,97,128,139],"system-level":[10],"fault-tolerance":[11],"techniques":[12,190],"such":[13],"as":[14],"error":[15],"correction":[16],"code":[17,77],"(ECC)":[18],"to":[19,45,71,75,83,92],"ensure":[20],"the":[21,29,54,69,94,98,136,150,173,181,194,203],"overall":[22],"system":[23,55,168,188],"storage":[24,30,39,56,101,141,154],"integrity.":[25],"Since":[26],"ECC":[27],"demands":[28],"of":[31,88,175,206],"coding":[32,49,60],"redundancy":[33],"hence":[35],"degrades":[36],"effective":[37],"cell":[38,100,140,153,216],"efficiency,":[40,102,155],"it":[41,86,146],"is":[42,87],"highly":[43],"desirable":[44],"use":[46],"more":[47],"powerful":[48],"solutions":[50],"that":[51,117,145,191,209],"can":[52,147,163,192,210],"maintain":[53],"reliability":[57],"at":[58],"less":[59],"redundancy.":[61],"This":[62],"has":[63],"motivated":[64,171],"a":[65],"growing":[66],"interest":[67],"in":[68,80,213],"industry":[70],"search":[72],"for":[73,134,167],"alternatives":[74],"BCH":[76],"being":[78],"used":[79],"today.":[81],"Regardless":[82],"specific":[84],"ECCs,":[85],"great":[89],"practical":[90],"importance":[91],"know":[93],"theoretical":[95],"limit":[96],"achievable":[99],"which":[103,129,162],"motivates":[104],"this":[105],"work.":[106],"We":[107,143],"first":[108],"develop":[109,132],"an":[110],"approximate":[111],"channel":[115],"model":[116],"explicitly":[118],"incorporates":[119],"program/erase":[120],"(P/E)":[121],"cycling":[122,157,177],"effects":[123],"cell-to-cell":[125],"interference,":[126],"based":[127],"we":[130,184],"then":[131],"strategies":[133],"estimating":[135],"information-theoretical":[137,182],"bounds":[138],"efficiency.":[142],"show":[144],"readily":[148],"reveal":[149],"tradeoffs":[151],"among":[152],"P/E":[156,176],"endurance,":[158],"retention":[160],"limit,":[161],"provide":[164],"important":[165],"insights":[166],"designers.":[169],"Finally,":[170],"by":[172,180],"dynamics":[174],"effect":[178],"revealed":[179],"study,":[183],"propose":[185],"two":[186],"design":[189],"improve":[193],"average":[195],"programming":[199],"speed":[200],"increase":[202],"total":[204],"amount":[205],"user":[207],"data":[208],"be":[211],"stored":[212],"over":[217],"its":[218],"entire":[219],"lifetime.":[220]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":10},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":10},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}