{"id":"https://openalex.org/W2081286217","doi":"https://doi.org/10.1109/tvlsi.2011.2160463","title":"Portable, Flexible, and Scalable Soft Vector Processors","display_name":"Portable, Flexible, and Scalable Soft Vector Processors","publication_year":2011,"publication_date":"2011-08-03","ids":{"openalex":"https://openalex.org/W2081286217","doi":"https://doi.org/10.1109/tvlsi.2011.2160463","mag":"2081286217"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2160463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2160463","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009732949","display_name":"Peter Yiannacouras","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"P. Yiannacouras","raw_affiliation_strings":["Edward S. Sr. Rogers Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","Edward S. Sr. Rogers Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Edward S. Sr. Rogers Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Edward S. Sr. Rogers Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110755517","display_name":"J. Gregory Steffan","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. G. Steffan","raw_affiliation_strings":["Edward S. Sr. Rogers Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","Edward S. Sr. Rogers Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Edward S. Sr. Rogers Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Edward S. Sr. Rogers Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090184149","display_name":"Jonathan Rose","orcid":"https://orcid.org/0000-0002-3551-2175"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. Rose","raw_affiliation_strings":["Edward S. Sr. Rogers Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","Edward S. Sr. Rogers Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Edward S. Sr. Rogers Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Edward S. Sr. Rogers Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5009732949"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":3.0922,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.92054139,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"20","issue":"8","first_page":"1429","last_page":"1442"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8115968704223633},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8067240715026855},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.6828604340553284},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6451351642608643},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5657232999801636},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5419796705245972},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4764711856842041},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4733799993991852},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4716963768005371},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.46927013993263245},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4297091066837311},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4286803901195526},{"id":"https://openalex.org/keywords/vector-processor","display_name":"Vector processor","score":0.4265483319759369}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8115968704223633},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8067240715026855},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.6828604340553284},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6451351642608643},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5657232999801636},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5419796705245972},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4764711856842041},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4733799993991852},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4716963768005371},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.46927013993263245},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4297091066837311},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4286803901195526},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.4265483319759369},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2011.2160463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2160463","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.299.6197","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.299.6197","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~jayar/pubs/yiannacouras/yiannacourastvlsi12.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":48,"referenced_works":["https://openalex.org/W1493456587","https://openalex.org/W1508226573","https://openalex.org/W1509625038","https://openalex.org/W1543657314","https://openalex.org/W1555915743","https://openalex.org/W1564901611","https://openalex.org/W1578876327","https://openalex.org/W1977933385","https://openalex.org/W1995348478","https://openalex.org/W2002752493","https://openalex.org/W2014176254","https://openalex.org/W2016558956","https://openalex.org/W2024080903","https://openalex.org/W2040073568","https://openalex.org/W2048166678","https://openalex.org/W2062558947","https://openalex.org/W2068419076","https://openalex.org/W2096281944","https://openalex.org/W2097586424","https://openalex.org/W2098681688","https://openalex.org/W2102081656","https://openalex.org/W2111683449","https://openalex.org/W2113843141","https://openalex.org/W2121076909","https://openalex.org/W2128602802","https://openalex.org/W2128748139","https://openalex.org/W2129565950","https://openalex.org/W2139836711","https://openalex.org/W2144481293","https://openalex.org/W2145947338","https://openalex.org/W2146449469","https://openalex.org/W2152687294","https://openalex.org/W2154881179","https://openalex.org/W2157855196","https://openalex.org/W2159717773","https://openalex.org/W2164215436","https://openalex.org/W2164361660","https://openalex.org/W2167897136","https://openalex.org/W2187559497","https://openalex.org/W2725179571","https://openalex.org/W2913795363","https://openalex.org/W3014482339","https://openalex.org/W4242532423","https://openalex.org/W4250330962","https://openalex.org/W4251809495","https://openalex.org/W6630653458","https://openalex.org/W6678876518","https://openalex.org/W6679300470"],"related_works":["https://openalex.org/W107105315","https://openalex.org/W1584537303","https://openalex.org/W1872724644","https://openalex.org/W2750549761","https://openalex.org/W4388155270","https://openalex.org/W28826848","https://openalex.org/W2122272819","https://openalex.org/W4367156293","https://openalex.org/W2148031998","https://openalex.org/W2156607773"],"abstract_inverted_index":{"Field-programmable":[0],"gate":[1],"arrays":[2],"(FPGAs)":[3],"are":[4],"increasingly":[5],"used":[6],"to":[7,17,67,79,94,154,159,167],"implement":[8,194],"embedded":[9,103],"digital":[10],"systems,":[11],"however,":[12],"the":[13,40,48,69,96,121],"hardware":[14,27,124,201],"design":[15,28,171],"necessary":[16],"do":[18],"so":[19],"is":[20,45,66,142,152],"time-consuming":[21],"and":[22,61,145,176,191],"tedious.":[23],"The":[24],"amount":[25],"of":[26,71],"can":[29,110,184,189],"be":[30],"reduced":[31],"by":[32],"employing":[33],"a":[34,53,106,117,169],"microprocessor":[35,44],"for":[36,123],"less-critical":[37],"computation":[38],"in":[39,101],"system.":[41],"Often":[42],"this":[43,84,128],"implemented":[46],"using":[47],"FPGA":[49,149,179,200],"reprogrammable":[50],"fabric":[51],"as":[52],"soft":[54,73,89,107,137,181],"processor":[55,109,138],"which":[56,141,188],"presently":[57],"have":[58],"simple":[59],"architectures":[60,187],"moderate":[62],"performance.":[63],"Our":[64],"goal":[65],"scale":[68,156],"performance":[70,157],"existing":[72],"processors":[74,90,183],"hence":[75,119],"expanding":[76],"their":[77],"suitability":[78],"more":[80,192],"critical":[81],"computation.":[82],"To":[83],"end":[85],"we":[86],"propose":[87],"extending":[88],"with":[91,134],"vector":[92,108,135,182],"extensions":[93],"exploit":[95],"abundant":[97],"data":[98,195],"parallelism":[99],"found":[100],"many":[102],"kernels.":[104],"Such":[105],"execute":[111],"these":[112,174],"kernels":[113],"much":[114],"faster":[115],"than":[116],"single-core":[118],"reducing":[120],"need":[122],"implementations.":[125],"We":[126],"observe":[127],"improved":[129],"execution":[130],"speed":[131],"through":[132],"experimentation":[133],"extended":[136],"architecture":[139],"(VESPA)":[140],"designed,":[143],"implemented,":[144],"evaluated":[146],"on":[147],"real":[148],"hardware.":[150],"VESPA":[151],"shown":[153],"effectively":[155],"up":[158],"32":[160],"lanes,":[161],"while":[162],"providing":[163],"substantial":[164],"architectural":[165],"flexibility":[166],"create":[168],"fine-grained":[170],"space.":[172],"With":[173],"characteristics,":[175],"portability":[177],"across":[178],"devices,":[180],"provide":[185],"exact-fit":[186],"efficiently":[190],"easily":[193],"parallel":[196],"workloads":[197],"over":[198],"custom":[199],"design.":[202]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}