{"id":"https://openalex.org/W2104606487","doi":"https://doi.org/10.1109/tvlsi.2011.2153883","title":"Optimizing Floating Point Units in Hybrid FPGAs","display_name":"Optimizing Floating Point Units in Hybrid FPGAs","publication_year":2011,"publication_date":"2011-06-21","ids":{"openalex":"https://openalex.org/W2104606487","doi":"https://doi.org/10.1109/tvlsi.2011.2153883","mag":"2104606487"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2153883","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2153883","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024101337","display_name":"ChiWai Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"ChiWai Yu","raw_affiliation_strings":["Department of Computing, Imperial College London, London, UK","Dept. of Comput., Imperial Coll. London, London, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Comput., Imperial Coll. London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045144421","display_name":"Alastair Smith","orcid":"https://orcid.org/0000-0002-5291-1442"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Alastair M. Smith","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, South Kensington, UK","Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, South Kensington, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057940557","display_name":"Wayne Luk","orcid":"https://orcid.org/0000-0002-6750-927X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Department of Computing, Imperial College London, London, UK","Dept. of Comput., Imperial Coll. London, London, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Comput., Imperial Coll. London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107994859","display_name":"Philip H. W. Leong","orcid":"https://orcid.org/0000-0002-3923-3499"},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"The University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Philip H. W. Leong","raw_affiliation_strings":["School of Electrical and Information Engineering, University of Sydney, Sydney, NSW, Australia","Sch. of Electr. & Inf. Eng., Univ. of Sidney, Sidney, NSW, Australia"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Information Engineering, University of Sydney, Sydney, NSW, Australia","institution_ids":["https://openalex.org/I129604602"]},{"raw_affiliation_string":"Sch. of Electr. & Inf. Eng., Univ. of Sidney, Sidney, NSW, Australia","institution_ids":["https://openalex.org/I129604602"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J. E. Wilton","raw_affiliation_strings":["School of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Sch. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5024101337"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":2.4314,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.8974713,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"20","issue":"7","first_page":"1295","last_page":"1303"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7460325956344604},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7385291457176208},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6981548070907593},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.6546565294265747},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.637530505657196},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.581469714641571},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.57349693775177},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5146197080612183},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5063184499740601},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4261079728603363},{"id":"https://openalex.org/keywords/floating-point-unit","display_name":"Floating-point unit","score":0.4169454872608185},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40569084882736206},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39183855056762695},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3557093143463135},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18903934955596924},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.12123376131057739},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09677731990814209}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7460325956344604},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7385291457176208},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6981548070907593},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.6546565294265747},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.637530505657196},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.581469714641571},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.57349693775177},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5146197080612183},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5063184499740601},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4261079728603363},{"id":"https://openalex.org/C110305270","wikidata":"https://www.wikidata.org/wiki/Q733507","display_name":"Floating-point unit","level":3,"score":0.4169454872608185},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40569084882736206},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39183855056762695},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3557093143463135},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18903934955596924},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.12123376131057739},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09677731990814209},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2011.2153883","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2153883","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.310.1445","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.310.1445","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.doc.ic.ac.uk/~wl/papers/12/tvlsi12cy.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1520019936","https://openalex.org/W1523051745","https://openalex.org/W1573000522","https://openalex.org/W1861262881","https://openalex.org/W1977850862","https://openalex.org/W1986507733","https://openalex.org/W2004940452","https://openalex.org/W2008694370","https://openalex.org/W2043510289","https://openalex.org/W2049548876","https://openalex.org/W2081967047","https://openalex.org/W2106942255","https://openalex.org/W2111800814","https://openalex.org/W2119981612","https://openalex.org/W2131770711","https://openalex.org/W2135436831","https://openalex.org/W2142676556","https://openalex.org/W2154900953","https://openalex.org/W2157618882","https://openalex.org/W2166062472","https://openalex.org/W2168020750","https://openalex.org/W2170245550"],"related_works":["https://openalex.org/W2155289750","https://openalex.org/W2024574431","https://openalex.org/W2117300767","https://openalex.org/W2510992755","https://openalex.org/W2374017528","https://openalex.org/W2541658314","https://openalex.org/W4285503609","https://openalex.org/W579454177","https://openalex.org/W3037505396","https://openalex.org/W2185692674"],"abstract_inverted_index":{"This":[0,116],"paper":[1],"introduces":[2],"a":[3,13,24,76,124],"methodology":[4,118],"to":[5,57,122],"optimize":[6],"coarse-grained":[7,107],"floating":[8,28,79],"point":[9,29,49,80],"units":[10],"(FPUs)":[11],"in":[12,94],"hybrid":[14],"field-programmable":[15],"gate":[16],"array":[17],"(FPGA),":[18],"where":[19],"the":[20,59,69,86,133,148],"FPU":[21,66,90,108,127,135],"consists":[22],"of":[23,26,62,78,89,96,126,150],"number":[25],"interconnected":[27],"adders/subtracters":[30],"(FAs),":[31],"multipliers":[32],"(FMs),":[33],"and":[34,41,67,72,92,99,113,155],"wordblocks":[35,38],"(WBs).":[36],"The":[37,130],"include":[39],"registers":[40],"lookup":[42],"tables":[43],"(LUTs)":[44],"which":[45],"can":[46,119],"implement":[47],"fixed":[48],"operations":[50],"efficiently.":[51],"We":[52,83],"employ":[53],"common":[54],"subgraph":[55],"extraction":[56],"determine":[58],"best":[60],"mix":[61],"blocks":[63],"within":[64],"an":[65,105],"study":[68],"area,":[70,97,152],"speed":[71],"utilization":[73],"tradeoff":[74],"over":[75],"set":[77],"benchmark":[81],"circuits.":[82],"then":[84],"explore":[85],"system":[87],"impact":[88],"density":[91,142],"flexibility":[93],"terms":[95],"speed,":[98],"routing":[100],"resources.":[101],"Finally,":[102],"we":[103],"derive":[104],"optimized":[106],"by":[109],"considering":[110],"both":[111],"architectural":[112],"system-level":[114],"issues.":[115],"proposed":[117],"be":[120],"used":[121],"evaluate":[123],"variety":[125],"architecture":[128,136],"optimizations.":[129],"results":[131],"for":[132],"selected":[134],"optimization":[137],"show":[138],"that":[139],"although":[140],"high":[141],"FPUs":[143],"are":[144],"slower,":[145],"they":[146],"have":[147],"advantages":[149],"improved":[151],"area-delay":[153],"product,":[154],"throughput.":[156]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}