{"id":"https://openalex.org/W2047120166","doi":"https://doi.org/10.1109/tvlsi.2011.2145423","title":"Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA","display_name":"Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA","publication_year":2011,"publication_date":"2011-05-25","ids":{"openalex":"https://openalex.org/W2047120166","doi":"https://doi.org/10.1109/tvlsi.2011.2145423","mag":"2047120166"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2145423","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2145423","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001763650","display_name":"Francisco Barranco","orcid":"https://orcid.org/0000-0002-3721-0170"},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Francisco Barranco","raw_affiliation_strings":["Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066297662","display_name":"Matteo Tomasi","orcid":null},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Matteo Tomasi","raw_affiliation_strings":["Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068832875","display_name":"Javier D\u00edaz","orcid":"https://orcid.org/0000-0002-1849-8068"},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Javier Diaz","raw_affiliation_strings":["Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011828222","display_name":"Mauricio Vanegas","orcid":"https://orcid.org/0000-0002-1370-2437"},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]},{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["ES","IT"],"is_corresponding":false,"raw_author_name":"Mauricio Vanegas","raw_affiliation_strings":["Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain","PSPC Group, Department of Biophysical and Electronic Engineering (DIBE), University of Genoa, Genoa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]},{"raw_affiliation_string":"PSPC Group, Department of Biophysical and Electronic Engineering (DIBE), University of Genoa, Genoa, Italy","institution_ids":["https://openalex.org/I83816512"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101663021","display_name":"Eduardo Ros","orcid":"https://orcid.org/0000-0001-6613-5256"},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Eduardo Ros","raw_affiliation_strings":["Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.4068,"has_fulltext":false,"cited_by_count":71,"citation_normalized_percentile":{"value":0.96551,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"20","issue":"6","first_page":"1058","last_page":"1067"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11105","display_name":"Advanced Image Processing Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13579","display_name":"Image and Video Stabilization","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8469798564910889},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7228922247886658},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7134842872619629},{"id":"https://openalex.org/keywords/optical-flow","display_name":"Optical flow","score":0.6231206655502319},{"id":"https://openalex.org/keywords/motion-estimation","display_name":"Motion estimation","score":0.6046602129936218},{"id":"https://openalex.org/keywords/scale","display_name":"Scale (ratio)","score":0.4981532096862793},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47425997257232666},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.46959391236305237},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4613381326198578},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4214560389518738},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38012462854385376},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3587333858013153},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3225453794002533},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32118985056877136},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3023068308830261},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1680743396282196},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.10706254839897156}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8469798564910889},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7228922247886658},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7134842872619629},{"id":"https://openalex.org/C155542232","wikidata":"https://www.wikidata.org/wiki/Q736111","display_name":"Optical flow","level":3,"score":0.6231206655502319},{"id":"https://openalex.org/C10161872","wikidata":"https://www.wikidata.org/wiki/Q557891","display_name":"Motion estimation","level":2,"score":0.6046602129936218},{"id":"https://openalex.org/C2778755073","wikidata":"https://www.wikidata.org/wiki/Q10858537","display_name":"Scale (ratio)","level":2,"score":0.4981532096862793},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47425997257232666},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.46959391236305237},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4613381326198578},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4214560389518738},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38012462854385376},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3587333858013153},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3225453794002533},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32118985056877136},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3023068308830261},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1680743396282196},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.10706254839897156},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2011.2145423","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2145423","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:iris.unige.it:11567/779038","is_oa":false,"landing_page_url":"http://hdl.handle.net/11567/779038","pdf_url":null,"source":{"id":"https://openalex.org/S4377196291","display_name":"CINECA IRIS Institutial Research Information System (University of Genoa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I83816512","host_organization_name":"University of Genoa","host_organization_lineage":["https://openalex.org/I83816512"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5099999904632568,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":52,"referenced_works":["https://openalex.org/W66708504","https://openalex.org/W181449048","https://openalex.org/W1496316025","https://openalex.org/W1501711475","https://openalex.org/W1548213442","https://openalex.org/W1565206031","https://openalex.org/W1578285471","https://openalex.org/W1578521870","https://openalex.org/W1620756601","https://openalex.org/W1692224744","https://openalex.org/W1938714998","https://openalex.org/W2030840811","https://openalex.org/W2040864360","https://openalex.org/W2041880269","https://openalex.org/W2050709002","https://openalex.org/W2093488518","https://openalex.org/W2096503284","https://openalex.org/W2097293837","https://openalex.org/W2097831436","https://openalex.org/W2098579890","https://openalex.org/W2099914474","https://openalex.org/W2100622342","https://openalex.org/W2103504761","https://openalex.org/W2103876808","https://openalex.org/W2104821808","https://openalex.org/W2107252836","https://openalex.org/W2108177213","https://openalex.org/W2111858817","https://openalex.org/W2116759740","https://openalex.org/W2118877769","https://openalex.org/W2119310316","https://openalex.org/W2120507162","https://openalex.org/W2129023304","https://openalex.org/W2133235718","https://openalex.org/W2141277095","https://openalex.org/W2145022254","https://openalex.org/W2145451652","https://openalex.org/W2154555084","https://openalex.org/W2157828724","https://openalex.org/W2169009388","https://openalex.org/W2169574628","https://openalex.org/W2531394286","https://openalex.org/W2751023760","https://openalex.org/W2914331897","https://openalex.org/W3003662786","https://openalex.org/W4243970992","https://openalex.org/W4285719527","https://openalex.org/W6607454471","https://openalex.org/W6629585808","https://openalex.org/W6634634177","https://openalex.org/W6677548441","https://openalex.org/W7006031011"],"related_works":["https://openalex.org/W4386083130","https://openalex.org/W2117442182","https://openalex.org/W3111737715","https://openalex.org/W2069571255","https://openalex.org/W3125517176","https://openalex.org/W2023355163","https://openalex.org/W2030154815","https://openalex.org/W2051121715","https://openalex.org/W1929254672","https://openalex.org/W4210264611"],"abstract_inverted_index":{"The":[0],"proposed":[1],"work":[2],"presents":[3],"a":[4,32,47,73,92],"highly":[5],"parallel":[6],"architecture":[7],"for":[8,24,46,65,72],"motion":[9,29],"estimation.":[10],"Our":[11,39],"system":[12,40,79],"implements":[13],"the":[14,21,25,53,57,66,70,78,82,85,97],"well-known":[15,88],"Lucas":[16],"and":[17,60,95],"Kanade":[18],"algorithm":[19],"with":[20,87],"multi-scale":[22,67],"extension":[23],"computation":[26],"of":[27,56,84],"large":[28],"estimations":[30],"in":[31,52],"dedicated":[33],"device":[34],"[field-programmable":[35],"gate":[36],"array":[37],"(FPGA)].":[38],"achieves":[41],"270":[42],"frames":[43,62],"per":[44,63],"second":[45,64],"640":[48],"\u00d7":[49],"480":[50],"resolution":[51],"best":[54],"case":[55],"mono-scale":[58],"implementation":[59],"32":[61],"one,":[68],"fulfilling":[69],"requirements":[71],"real-time":[74],"system.":[75],"We":[76],"describe":[77],"architecture,":[80],"address":[81],"evaluation":[83],"accuracy":[86],"benchmark":[89],"sequences":[90],"(including":[91],"comparative":[93],"study),":[94],"show":[96],"main":[98],"hardware":[99],"resources":[100],"used.":[101]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":12},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}