{"id":"https://openalex.org/W2090662896","doi":"https://doi.org/10.1109/tvlsi.2011.2142202","title":"Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches","display_name":"Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches","publication_year":2011,"publication_date":"2011-05-13","ids":{"openalex":"https://openalex.org/W2090662896","doi":"https://doi.org/10.1109/tvlsi.2011.2142202","mag":"2090662896"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2142202","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2142202","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/10251/34853","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001423758","display_name":"Alejandro Valero","orcid":"https://orcid.org/0000-0002-0824-5833"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Alejandro Valero","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390347","display_name":"Julio Sahuquillo","orcid":"https://orcid.org/0000-0001-8630-4846"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Julio Sahuquillo","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008389350","display_name":"Vicente Lorente","orcid":"https://orcid.org/0000-0001-9466-2395"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Vicente Lorente","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013237315","display_name":"Salvador Petit","orcid":"https://orcid.org/0000-0003-2426-4134"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Salvador Petit","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101612028","display_name":"Pedro L\u00f3pez","orcid":"https://orcid.org/0000-0003-4544-955X"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Lopez","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040384183","display_name":"J. Duato","orcid":"https://orcid.org/0000-0002-7785-0607"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jos\u00e9 Duato","raw_affiliation_strings":["Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering (DISCA), Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5001423758"],"corresponding_institution_ids":["https://openalex.org/I60053951"],"apc_list":null,"apc_paid":null,"fwci":1.0075,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.77818078,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"20","issue":"6","first_page":"1108","last_page":"1117"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/macrocell","display_name":"Macrocell","score":0.9346383810043335},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7778743505477905},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6897886395454407},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6337098479270935},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.606444239616394},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.5568921566009521},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.541612446308136},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.4312213659286499},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.41019803285598755},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40087807178497314},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26669377088546753},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.26239269971847534},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.2502260208129883},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2451658546924591},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17397868633270264},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.164126455783844},{"id":"https://openalex.org/keywords/chemistry","display_name":"Chemistry","score":0.08828243613243103},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.06983157992362976}],"concepts":[{"id":"https://openalex.org/C2778291847","wikidata":"https://www.wikidata.org/wiki/Q1163937","display_name":"Macrocell","level":3,"score":0.9346383810043335},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7778743505477905},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6897886395454407},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6337098479270935},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.606444239616394},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.5568921566009521},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.541612446308136},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.4312213659286499},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.41019803285598755},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40087807178497314},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26669377088546753},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.26239269971847534},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.2502260208129883},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2451658546924591},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17397868633270264},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.164126455783844},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.08828243613243103},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.06983157992362976},{"id":"https://openalex.org/C147789679","wikidata":"https://www.wikidata.org/wiki/Q11372","display_name":"Physical chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C68649174","wikidata":"https://www.wikidata.org/wiki/Q1379116","display_name":"Base station","level":2,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2011.2142202","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2142202","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:riunet.upv.es:10251/34853","is_oa":true,"landing_page_url":"http://hdl.handle.net/10251/34853","pdf_url":null,"source":{"id":"https://openalex.org/S4306401500","display_name":"RiuNet (Politechnical University of Valencia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I60053951","host_organization_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","host_organization_lineage":["https://openalex.org/I60053951"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:riunet.upv.es:10251/34853","is_oa":true,"landing_page_url":"http://hdl.handle.net/10251/34853","pdf_url":null,"source":{"id":"https://openalex.org/S4306401500","display_name":"RiuNet (Politechnical University of Valencia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I60053951","host_organization_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","host_organization_lineage":["https://openalex.org/I60053951"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1550928833","https://openalex.org/W1965522623","https://openalex.org/W1970454100","https://openalex.org/W2023062763","https://openalex.org/W2038061869","https://openalex.org/W2064037464","https://openalex.org/W2064977311","https://openalex.org/W2098040113","https://openalex.org/W2100799944","https://openalex.org/W2105102111","https://openalex.org/W2105407012","https://openalex.org/W2110999128","https://openalex.org/W2114429886","https://openalex.org/W2126357937","https://openalex.org/W2131054871","https://openalex.org/W2135885084","https://openalex.org/W2158199659","https://openalex.org/W2159253302","https://openalex.org/W2916411819","https://openalex.org/W3145579537","https://openalex.org/W3147067924","https://openalex.org/W4235106764","https://openalex.org/W4248310916","https://openalex.org/W4253202538","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2186949690","https://openalex.org/W2167303720","https://openalex.org/W2549803267","https://openalex.org/W2497617944","https://openalex.org/W3019064768","https://openalex.org/W1563139915","https://openalex.org/W3019683061","https://openalex.org/W2132842408","https://openalex.org/W2109715593","https://openalex.org/W2954442117"],"abstract_inverted_index":{"Cache":[0],"memories":[1],"dissipate":[2],"an":[3],"important":[4],"amount":[5],"of":[6,38,68,78,110,159,219],"the":[7,36,66,74,94,111,125,141,152,167,217],"energy":[8,70,83,120,130,157,187],"budget":[9],"in":[10,54],"current":[11],"microprocessors.":[12],"This":[13,58,138],"is":[14,127],"mainly":[15],"due":[16],"to":[17,176,191],"cache":[18,40,47,162,195],"cells":[19,80,89],"are":[20,182,189],"typically":[21],"implemented":[22],"with":[23,65,196],"six":[24],"transistors.":[25],"To":[26,149],"tackle":[27],"this":[28,150],"design":[29],"concern,":[30],"recent":[31],"research":[32],"has":[33,51,163],"focused":[34],"on":[35,82,117],"proposal":[37],"new":[39],"cells.":[41,223],"An":[42],"<i":[43],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[44],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">n</i>":[45],"-bit":[46],"cell,":[48],"namely":[49],"macrocell,":[50],"been":[52,164],"proposed":[53],"a":[55,100,107,145,160,177,194,211],"previous":[56],"work.":[57],"cell":[59],"combines":[60],"SRAM":[61,222],"and":[62,85,119,156,169,186,200],"eDRAM":[63,79],"technologies":[64],"aim":[67],"reducing":[69],"consumption":[71,84,158],"while":[72],"maintaining":[73],"performance.":[75],"The":[76],"capacitance":[77,126,143,168],"impacts":[81],"performance":[86,118,136,155,180],"since":[87],"these":[88],"lose":[90],"their":[91],"state":[92],"once":[93],"retention":[95],"time":[96],"expires.":[97],"On":[98],"such":[99],"case,":[101],"data":[102],"must":[103],"be":[104,132],"fetched":[105],"from":[106],"lower":[108,183],"level":[109],"memory":[112],"hierarchy,":[113],"so":[114],"negatively":[115],"impacting":[116],"consumption.":[121],"As":[122],"opposite,":[123],"if":[124],"too":[128],"high,":[129],"would":[131],"wasted":[133],"without":[134],"bringing":[135],"benefits.":[137],"paper":[139],"identifies":[140],"optimal":[142],"for":[144,193],"given":[146],"processor":[147],"frequency.":[148,170],"end,":[151],"tradeoff":[153],"between":[154],"macrocell-based":[161],"evaluated":[165],"varying":[166],"Experimental":[171],"results":[172],"show":[173],"that,":[174],"compared":[175],"conventional":[178,221],"cache,":[179],"losses":[181],"than":[184,203],"2%":[185],"savings":[188],"up":[190],"55%":[192],"10":[197],"fF":[198],"capacitors":[199],"frequencies":[201],"higher":[202],"1":[204],"GHz.":[205],"In":[206],"addition,":[207],"using":[208],"trench":[209],"capacitors,":[210],"4-bit":[212],"macrocell":[213],"reduces":[214],"by":[215],"29%":[216],"area":[218],"four":[220]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}