{"id":"https://openalex.org/W2003105949","doi":"https://doi.org/10.1109/tvlsi.2011.2135868","title":"CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations","display_name":"CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations","publication_year":2011,"publication_date":"2011-05-09","ids":{"openalex":"https://openalex.org/W2003105949","doi":"https://doi.org/10.1109/tvlsi.2011.2135868","mag":"2003105949"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2135868","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2135868","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045869255","display_name":"W. Paul Griffin","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. Paul Griffin","raw_affiliation_strings":["Department of Electrical Engineering, Purdue University, West Lafayette, IN, USA","[Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA]","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065766721","display_name":"Anand Raghunathan","orcid":"https://orcid.org/0000-0002-4624-564X"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anand Raghunathan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046257293","display_name":"Kaushik Roy","orcid":"https://orcid.org/0000-0003-4937-2115"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":1.7704,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.85131443,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"20","issue":"5","first_page":"791","last_page":"803"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9786999821662903,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6701391935348511},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6333221197128296},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6049460172653198},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5713873505592346},{"id":"https://openalex.org/keywords/hardware-security-module","display_name":"Hardware security module","score":0.5466729402542114},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5107734203338623},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.48877593874931335},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.48118239641189575},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4600825607776642},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4591893255710602},{"id":"https://openalex.org/keywords/semiconductor-device-fabrication","display_name":"Semiconductor device fabrication","score":0.4304143190383911},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42124325037002563},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.41833022236824036},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4144613742828369},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26542896032333374},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21081390976905823},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.12426114082336426},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08902522921562195},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.07552042603492737}],"concepts":[{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6701391935348511},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6333221197128296},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6049460172653198},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5713873505592346},{"id":"https://openalex.org/C39217717","wikidata":"https://www.wikidata.org/wiki/Q1432354","display_name":"Hardware security module","level":3,"score":0.5466729402542114},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5107734203338623},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.48877593874931335},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.48118239641189575},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4600825607776642},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4591893255710602},{"id":"https://openalex.org/C66018809","wikidata":"https://www.wikidata.org/wiki/Q1570432","display_name":"Semiconductor device fabrication","level":3,"score":0.4304143190383911},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42124325037002563},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.41833022236824036},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4144613742828369},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26542896032333374},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21081390976905823},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.12426114082336426},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08902522921562195},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.07552042603492737},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2135868","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2135868","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6100000143051147,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":48,"referenced_works":["https://openalex.org/W42545666","https://openalex.org/W186555678","https://openalex.org/W1565539145","https://openalex.org/W1629301835","https://openalex.org/W1661368752","https://openalex.org/W1986199670","https://openalex.org/W1987476244","https://openalex.org/W1995871244","https://openalex.org/W2012725064","https://openalex.org/W2019967639","https://openalex.org/W2028522822","https://openalex.org/W2029247117","https://openalex.org/W2042809000","https://openalex.org/W2099528297","https://openalex.org/W2104160351","https://openalex.org/W2106409910","https://openalex.org/W2106722176","https://openalex.org/W2116590916","https://openalex.org/W2119964970","https://openalex.org/W2121141110","https://openalex.org/W2130351941","https://openalex.org/W2133305741","https://openalex.org/W2138874069","https://openalex.org/W2144630005","https://openalex.org/W2145771994","https://openalex.org/W2146832742","https://openalex.org/W2154909745","https://openalex.org/W2156420172","https://openalex.org/W2157809350","https://openalex.org/W2167381458","https://openalex.org/W2169212403","https://openalex.org/W2170047587","https://openalex.org/W2170623172","https://openalex.org/W2293877751","https://openalex.org/W2971250997","https://openalex.org/W3144121041","https://openalex.org/W3150532282","https://openalex.org/W4230572467","https://openalex.org/W4231098049","https://openalex.org/W4237823503","https://openalex.org/W4242424853","https://openalex.org/W4251100134","https://openalex.org/W4252479895","https://openalex.org/W6633762270","https://openalex.org/W6675797392","https://openalex.org/W6679357471","https://openalex.org/W6681477738","https://openalex.org/W6682554491"],"related_works":["https://openalex.org/W1952517978","https://openalex.org/W2677867825","https://openalex.org/W1984922722","https://openalex.org/W1849713424","https://openalex.org/W4386021186","https://openalex.org/W2092166371","https://openalex.org/W2146978563","https://openalex.org/W2787752683","https://openalex.org/W2465780682","https://openalex.org/W2101197344"],"abstract_inverted_index":{"The":[0],"disaggregation":[1],"of":[2,44,71,103,131,148,167,209,228],"the":[3,21,38,48,51,63,69,72,76,101,115,146,154,159,165,168,179,207,210],"semiconductor":[4,22],"design":[5,64],"and":[6,61,133,140,182,217],"manufacturing":[7],"process":[8,45,57],"has":[9],"resulted":[10],"in":[11,199],"integrated":[12],"circuit":[13,39,52],"(IC)":[14],"piracy":[15],"becoming":[16],"an":[17],"important":[18],"concern":[19],"to":[20,67,106,113,124,152,178,189],"industry.":[23],"To":[24],"address":[25],"this":[26],"concern,":[27],"we":[28],"present":[29],"a":[30,83,92,122,149,185,200,225],"method":[31],"for":[32,196],"achieving":[33],"robust":[34,222],"IC":[35,87],"protection":[36,223],"at":[37,78],"level":[40],"through":[41],"direct":[42],"injection":[43,132],"variations.":[46],"In":[47],"proposed":[49,169,211],"approach,":[50],"is":[53,88,97,111,176],"enhanced":[54],"by":[55,128],"including":[56],"variation":[58],"(PV)":[59],"sensors":[60,74],"modifying":[62],"during":[65],"synthesis":[66],"inject":[68],"outputs":[70],"PV":[73],"into":[75],"logic":[77],"carefully":[79],"selected":[80],"nodes.":[81],"As":[82],"result,":[84],"each":[85,104],"fabricated":[86],"rendered":[89],"inoperative":[90],"unless":[91],"unique":[93],"per-chip":[94,117],"unlocking":[95,118,161],"key":[96,156,180],"applied.":[98],"After":[99],"fabrication,":[100],"response":[102],"chip":[105],"specially":[107],"generated":[108],"test":[109],"vectors":[110],"used":[112,157],"construct":[114],"correct":[116],"key.":[119],"We":[120,144,205],"propose":[121,145],"methodology":[123,175],"automatically":[125],"modify":[126],"circuits":[127],"identifying":[129],"pairs":[130],"correction":[134],"points,":[135],"while":[136],"avoiding":[137],"delay":[138],"penalty":[139],"minimizing":[141],"area":[142,187],"overheads.":[143],"use":[147],"cryptographic":[150],"preprocessor":[151],"separate":[153],"internal":[155],"from":[158],"external":[160],"key,":[162],"further":[163],"enhancing":[164],"resistance":[166],"approach":[170],"against":[171,224],"several":[172,214],"attacks.":[173,229],"Our":[174],"scalable":[177],"size":[181],"requires":[183],"only":[184],"small":[186],"overhead":[188],"achieve":[190],"reasonable":[191],"security":[192,208],"levels":[193],"(e.g.,":[194],"7%":[195],"64-bit":[197],"keys":[198],"8":[201],"k":[202],"gate":[203],"design).":[204],"analyze":[206],"technique":[212],"under":[213],"attack":[215],"scenarios":[216],"believe":[218],"that":[219],"it":[220],"offers":[221],"wide":[226],"range":[227]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}