{"id":"https://openalex.org/W1991804702","doi":"https://doi.org/10.1109/tvlsi.2011.2134875","title":"Single Cycle Access Structure for Logic Test","display_name":"Single Cycle Access Structure for Logic Test","publication_year":2011,"publication_date":"2011-04-26","ids":{"openalex":"https://openalex.org/W1991804702","doi":"https://doi.org/10.1109/tvlsi.2011.2134875","mag":"1991804702"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2134875","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2134875","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039814764","display_name":"Tobias Strauch","orcid":"https://orcid.org/0000-0002-5430-8700"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Tobias Strauch","raw_affiliation_strings":["Research and Development, EDAptability e.K, Munich, Germany","R&D, EDAptability e.K., Munich, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Research and Development, EDAptability e.K, Munich, Germany","institution_ids":[]},{"raw_affiliation_string":"R&D, EDAptability e.K., Munich, Germany#TAB#","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5039814764"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.96671824,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.7705738,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"20","issue":"5","first_page":"878","last_page":"891"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9912999868392944,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.8073121309280396},{"id":"https://openalex.org/keywords/digital-pattern-generator","display_name":"Digital pattern generator","score":0.6795527935028076},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6529879570007324},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6154334545135498},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.6065858602523804},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5977876782417297},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.5719337463378906},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5506057143211365},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.5385469198226929},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.49721649289131165},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4638059139251709},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4486095607280731},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.44827860593795776},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4146101772785187},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35482728481292725},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3512795567512512},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2506934404373169},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2144072949886322},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.16713541746139526},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1646784245967865},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.15070247650146484},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.094114750623703}],"concepts":[{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.8073121309280396},{"id":"https://openalex.org/C151346624","wikidata":"https://www.wikidata.org/wiki/Q5276129","display_name":"Digital pattern generator","level":3,"score":0.6795527935028076},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6529879570007324},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6154334545135498},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.6065858602523804},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5977876782417297},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.5719337463378906},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5506057143211365},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.5385469198226929},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.49721649289131165},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4638059139251709},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4486095607280731},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.44827860593795776},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4146101772785187},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35482728481292725},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3512795567512512},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2506934404373169},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2144072949886322},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.16713541746139526},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1646784245967865},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.15070247650146484},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.094114750623703},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2134875","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2134875","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W52459088","https://openalex.org/W1506569352","https://openalex.org/W1894414010","https://openalex.org/W1976944456","https://openalex.org/W1999522740","https://openalex.org/W2014671469","https://openalex.org/W2061373501","https://openalex.org/W2077562862","https://openalex.org/W2088993611","https://openalex.org/W2096441057","https://openalex.org/W2098411556","https://openalex.org/W2099575624","https://openalex.org/W2099761728","https://openalex.org/W2101900253","https://openalex.org/W2104769159","https://openalex.org/W2111569953","https://openalex.org/W2112129823","https://openalex.org/W2113809744","https://openalex.org/W2117891373","https://openalex.org/W2121466258","https://openalex.org/W2125054260","https://openalex.org/W2133456190","https://openalex.org/W2144852451","https://openalex.org/W2145579809","https://openalex.org/W2149124583","https://openalex.org/W2151577463","https://openalex.org/W2151601490","https://openalex.org/W2155798094","https://openalex.org/W2168446727","https://openalex.org/W3151372805","https://openalex.org/W4249524628","https://openalex.org/W6602054072","https://openalex.org/W6630264434","https://openalex.org/W6674775035","https://openalex.org/W6675059580"],"related_works":["https://openalex.org/W2188176208","https://openalex.org/W2154529098","https://openalex.org/W1598002399","https://openalex.org/W2119351822","https://openalex.org/W2123022840","https://openalex.org/W2914537975","https://openalex.org/W2130268465","https://openalex.org/W2184064278","https://openalex.org/W2105858357","https://openalex.org/W3131178091"],"abstract_inverted_index":{"This":[0,34],"paper":[1],"proposes":[2],"a":[3,71,92,157],"new":[4],"single":[5],"cycle":[6],"access":[7],"test":[8,50,75,86,94,99,148,172],"structure":[9,126],"for":[10,105,134],"logic":[11],"test.":[12],"It":[13,46,66,160],"eliminates":[14],"the":[15,27,48,61,112,166],"peak":[16],"power":[17],"consumption":[18],"problem":[19],"of":[20,74,111],"conventional":[21],"shift-based":[22],"scan":[23,144,177],"chains":[24],"and":[25,31,43,108,146,151,174],"reduces":[26],"activity":[28],"during":[29,41],"shift":[30],"capture":[32],"cycles.":[33],"leads":[35],"to":[36,51,60,81,118,142,164],"more":[37],"realistic":[38],"circuit":[39],"behavior":[40],"stuck-at":[42],"at-speed":[44],"tests.":[45],"enables":[47],"complete":[49],"run":[52],"at":[53],"much":[54],"higher":[55],"frequencies":[56],"equal":[57],"or":[58],"close":[59],"one":[62],"in":[63],"functional":[64],"mode.":[65],"will":[67],"be":[68,78,154],"shown,":[69],"that":[70],"lesser":[72],"number":[73],"cycles":[76,87],"can":[77,153],"achieved":[79],"compared":[80,117],"other":[82,119],"published":[83,120],"solutions.":[84],"The":[85,125,137],"per":[88],"net":[89],"based":[90],"on":[91,122],"simple":[93],"pattern":[95,100,149],"generator":[96],"algorithm":[97],"without":[98],"compression":[101],"is":[102,109,139,161],"below":[103],"1":[104],"larger":[106],"designs":[107,145],"independent":[110],"design":[113],"size.":[114],"Results":[115],"are":[116],"solutions":[121],"ISCAS'89":[123],"netlists.":[124],"allows":[127],"an":[128],"additional":[129],"on-chip":[130],"debugging":[131],"signal":[132],"visibility":[133],"each":[135],"register.":[136],"method":[138],"backward":[140],"compatible":[141],"full":[143],"existing":[147],"generators":[150],"simulators":[152],"used":[155],"with":[156,169],"minor":[158],"enhancement.":[159],"shown":[162],"how":[163],"combine":[165],"proposed":[167],"solution":[168],"built-in":[170],"self":[171],"(BIST)":[173],"massive":[175],"parallel":[176],"chains.":[178]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}