{"id":"https://openalex.org/W1970556373","doi":"https://doi.org/10.1109/tvlsi.2011.2110620","title":"A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy","display_name":"A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy","publication_year":2011,"publication_date":"2011-03-02","ids":{"openalex":"https://openalex.org/W1970556373","doi":"https://doi.org/10.1109/tvlsi.2011.2110620","mag":"1970556373"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2110620","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2110620","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059884632","display_name":"Yuan\u2010Ho Chen","orcid":"https://orcid.org/0000-0001-5651-7584"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yuan-Ho Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100885664","display_name":"Tsin\u2010Yuan Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsin-Yuan Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5059884632"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":2.4498,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.89107725,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"20","issue":"4","first_page":"655","last_page":"664"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6701613068580627},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.6282321214675903},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5980967283248901},{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.5219411253929138},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.4515220522880554},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44631677865982056},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4344369173049927},{"id":"https://openalex.org/keywords/gate-count","display_name":"Gate count","score":0.4330289661884308},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41558173298835754},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35299813747406006},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.34243088960647583},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.2536986470222473},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.1685154139995575},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16851043701171875},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14181587100028992}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6701613068580627},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.6282321214675903},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5980967283248901},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.5219411253929138},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.4515220522880554},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44631677865982056},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4344369173049927},{"id":"https://openalex.org/C2777892113","wikidata":"https://www.wikidata.org/wiki/Q5527005","display_name":"Gate count","level":2,"score":0.4330289661884308},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41558173298835754},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35299813747406006},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.34243088960647583},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.2536986470222473},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.1685154139995575},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16851043701171875},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14181587100028992},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2110620","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2110620","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1481550144","https://openalex.org/W1492380776","https://openalex.org/W1514203438","https://openalex.org/W1561725608","https://openalex.org/W2065190499","https://openalex.org/W2066650353","https://openalex.org/W2103226167","https://openalex.org/W2103539323","https://openalex.org/W2104153638","https://openalex.org/W2104569669","https://openalex.org/W2108791478","https://openalex.org/W2114827318","https://openalex.org/W2125791563","https://openalex.org/W2128530460","https://openalex.org/W2131441307","https://openalex.org/W2136300693","https://openalex.org/W2139269844","https://openalex.org/W2148248162","https://openalex.org/W2148642242","https://openalex.org/W2163962121","https://openalex.org/W2172699263","https://openalex.org/W2534285044","https://openalex.org/W2917583897","https://openalex.org/W4244889501","https://openalex.org/W6678486160","https://openalex.org/W6678993071","https://openalex.org/W6679515122"],"related_works":["https://openalex.org/W2362169398","https://openalex.org/W2139353707","https://openalex.org/W3083915265","https://openalex.org/W2106127105","https://openalex.org/W2130715089","https://openalex.org/W3118502605","https://openalex.org/W2808532520","https://openalex.org/W4301955845","https://openalex.org/W3123827098","https://openalex.org/W2572327332"],"abstract_inverted_index":{"In":[0,105],"this":[1,132],"paper,":[2],"a":[3,41,80,113,143,147,155,177,184],"spatial":[4,27],"and":[5,50,66,146,151,188],"time":[6,53,129],"scheduling":[7,12,28,54],"strategy,":[8,14],"called":[9],"the":[10,31,35,47,51,96,107,120,127,134,174],"space-time":[11],"(STS)":[13],"that":[15,45,61,118,173],"achieves":[16,139],"high":[17,140,148],"image":[18,103],"resolutions":[19],"in":[20,60,70],"real-time":[21],"systems":[22],"is":[23,89,152,189],"proposed.":[24],"The":[25,85],"proposed":[26,52,108,135],"strategy":[29,55],"includes":[30],"ability":[32],"to":[33,78,123],"choose":[34],"distributed":[36],"arithmetic":[37,121],"(DA)-precision":[38],"bit":[39,87],"length,":[40],"hardware":[42,48,81,109],"sharing":[43,110],"architecture":[44,111,117],"reduces":[46],"cost,":[49],"arranges":[56],"different":[57],"dimensional":[58],"computations":[59],"it":[62],"can":[63],"calculate":[64],"first-dimensional":[65],"second-dimensional":[67],"transformations":[68],"simultaneously":[69],"single":[71],"1-D":[72],"discrete":[73],"cosine":[74],"transform":[75],"(DCT)":[76],"core":[77,138,175],"reach":[79],"utilization":[82],"of":[83,95,179],"100%.":[84],"DA-precision":[86],"length":[88],"chosen":[90],"as":[91],"9":[92],"bits":[93,99],"instead":[94],"traditional":[97],"12":[98],"based":[100],"on":[101],"test":[102],"simulations.":[104],"addition,":[106],"employs":[112],"binary":[114],"signed-digit":[115],"DA":[116],"enables":[119],"resources":[122],"be":[124],"shared":[125],"during":[126],"four":[128],"slots.":[130],"For":[131],"reason,":[133],"2-D":[136],"DCT":[137],"accuracy":[141],"with":[142,183,194],"small":[144],"area":[145],"throughput":[149],"rate":[150],"verified":[153],"using":[154],"TSMC":[156],"0.18-":[157],"<formula":[158],"formulatype=\"inline\"":[159],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[160],"xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex":[161],"Notation=\"TeX\">$\\mu$</tex>":[162],"</formula>":[163],"m":[164],"1P6M":[165],"CMOS":[166],"process":[167],"chip":[168],"implementation.":[169],"Measurement":[170],"results":[171],"show":[172],"has":[176],"latency":[178],"84":[180],"clock":[181],"cycles":[182],"52":[185],"dB":[186],"peak-signal-to-noise-ratio":[187],"operated":[190],"at":[191],"167":[192],"MHz":[193],"15.8":[195],"K":[196],"gate":[197],"counts.":[198]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
