{"id":"https://openalex.org/W2160301612","doi":"https://doi.org/10.1109/tvlsi.2011.2104983","title":"SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems","display_name":"SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems","publication_year":2011,"publication_date":"2011-02-03","ids":{"openalex":"https://openalex.org/W2160301612","doi":"https://doi.org/10.1109/tvlsi.2011.2104983","mag":"2160301612"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2011.2104983","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2104983","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091146878","display_name":"Jai-Ming Lin","orcid":"https://orcid.org/0000-0001-8637-2144"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Jai-Ming Lin","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110265340","display_name":"Zhi-Xiong Hung","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Zhi-Xiong Hung","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5091146878"],"corresponding_institution_ids":["https://openalex.org/I91807558"],"apc_list":null,"apc_paid":null,"fwci":1.5898,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.85540182,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"20","issue":"3","first_page":"473","last_page":"484"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9864000082015991,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9491000175476074,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.898339033126831},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5764211416244507},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.5441908836364746},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5236667990684509},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4638044834136963},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.43962469696998596},{"id":"https://openalex.org/keywords/steiner-tree-problem","display_name":"Steiner tree problem","score":0.42118072509765625},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.414937287569046},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3808221220970154},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3710538446903229},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3669286370277405},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.31784379482269287},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23681721091270447},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.14804357290267944},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09366908669471741}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.898339033126831},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5764211416244507},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.5441908836364746},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5236667990684509},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4638044834136963},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.43962469696998596},{"id":"https://openalex.org/C76220878","wikidata":"https://www.wikidata.org/wiki/Q1764144","display_name":"Steiner tree problem","level":2,"score":0.42118072509765625},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.414937287569046},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3808221220970154},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3710538446903229},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3669286370277405},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.31784379482269287},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23681721091270447},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.14804357290267944},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09366908669471741},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2011.2104983","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2011.2104983","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":57,"referenced_works":["https://openalex.org/W1702702848","https://openalex.org/W1967985871","https://openalex.org/W1993038918","https://openalex.org/W1993509482","https://openalex.org/W1999034258","https://openalex.org/W2007916227","https://openalex.org/W2021998347","https://openalex.org/W2024060531","https://openalex.org/W2055798429","https://openalex.org/W2073092303","https://openalex.org/W2074040368","https://openalex.org/W2082348718","https://openalex.org/W2082998942","https://openalex.org/W2094042791","https://openalex.org/W2095550547","https://openalex.org/W2098143668","https://openalex.org/W2100740271","https://openalex.org/W2106319297","https://openalex.org/W2109846948","https://openalex.org/W2110514755","https://openalex.org/W2110721922","https://openalex.org/W2113341980","https://openalex.org/W2113451265","https://openalex.org/W2114772983","https://openalex.org/W2117754533","https://openalex.org/W2127012874","https://openalex.org/W2139524433","https://openalex.org/W2140704214","https://openalex.org/W2141746747","https://openalex.org/W2143401110","https://openalex.org/W2144249008","https://openalex.org/W2144473140","https://openalex.org/W2148777220","https://openalex.org/W2149976210","https://openalex.org/W2153770483","https://openalex.org/W2156974682","https://openalex.org/W2162877164","https://openalex.org/W2166295488","https://openalex.org/W2168300107","https://openalex.org/W2168908650","https://openalex.org/W4205135025","https://openalex.org/W4230562647","https://openalex.org/W4234113102","https://openalex.org/W4236626993","https://openalex.org/W4238906052","https://openalex.org/W4238999275","https://openalex.org/W4239854918","https://openalex.org/W4242842879","https://openalex.org/W4248596413","https://openalex.org/W6637416867","https://openalex.org/W6652141237","https://openalex.org/W6664309405","https://openalex.org/W6668743019","https://openalex.org/W6674301526","https://openalex.org/W6678589545","https://openalex.org/W6680834781","https://openalex.org/W6682239439"],"related_works":["https://openalex.org/W2261987718","https://openalex.org/W2150188392","https://openalex.org/W1972630917","https://openalex.org/W4236115276","https://openalex.org/W2156728385","https://openalex.org/W2064869192","https://openalex.org/W1995846884","https://openalex.org/W2155595641","https://openalex.org/W4242017923","https://openalex.org/W2151294655"],"abstract_inverted_index":{"In":[0],"this":[1,53],"paper,":[2],"we":[3,56,71],"propose":[4],"an":[5],"SKB-tree":[6,19,110,122,150],"representation":[7,44],"for":[8,24,37,45,145],"two":[9],"modern":[10],"floorplaning":[11],"problems:":[12],"fixed-outline":[13,49,105,129],"and":[14,92,120,155],"voltage-island":[15,64],"driven":[16,65,130,148],"floorplanning.":[17,66],"Since":[18],"can":[20,30,123],"dynamically":[21],"allocate":[22],"regions":[23],"blocks":[25,29,73],"so":[26],"that":[27],"all":[28],"be":[31,79],"placed":[32,80],"into":[33,81],"a":[34,42],"specific":[35],"outline":[36],"each":[38],"solution,":[39],"it":[40,59,133],"is":[41],"suitable":[43],"dealing":[46],"with":[47,62,107],"the":[48,63,75,99,104],"constraint.":[50],"Due":[51],"to":[52,60,78,84,136],"good":[54],"property,":[55],"also":[57,151],"use":[58],"deal":[61],"Different":[67],"from":[68],"previous":[69],"works,":[70],"constrain":[72],"of":[74,101],"same":[76],"voltage":[77,146],"one":[82],"region":[83],"save":[85],"power":[86,90,154],"routing":[87],"resource,":[88],"simplify":[89],"planning,":[91],"reduce":[93],"IR":[94],"Drop.":[95],"Experimental":[96],"results":[97,126],"show":[98],"feasibility":[100],"SKB-tree.":[102],"For":[103],"constraint":[106],"zero":[108],"deadspace,":[109],"achieved":[111],"significantly":[112],"better":[113,125],"wirelength":[114,139],"than":[115,127],"A-FP,":[116],"Parquet":[117],"4.0,":[118],"ZDS,":[119],"SAFFOA.":[121],"get":[124],"other":[128],"floorplanners":[131],"because":[132],"only":[134],"needs":[135],"focus":[137],"on":[138],"optimization":[140],"during":[141],"simulated":[142],"annealing.":[143],"Besides,":[144],"island":[147],"floorplanning,":[149],"consumes":[152],"less":[153],"wirelength.":[156]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":4},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
