{"id":"https://openalex.org/W2170181037","doi":"https://doi.org/10.1109/tvlsi.2010.2103961","title":"High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes","display_name":"High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes","publication_year":2011,"publication_date":"2011-02-03","ids":{"openalex":"https://openalex.org/W2170181037","doi":"https://doi.org/10.1109/tvlsi.2010.2103961","mag":"2170181037"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2010.2103961","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2103961","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/10251/35462","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088891897","display_name":"Francisco Garc\u00eda-Herrero","orcid":"https://orcid.org/0000-0001-6719-9681"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"F. Garcia-Herrero","raw_affiliation_strings":["Universidad Polit\u00e9cnica de Valencia, Instituto de Telecomunicaciones y Aplicaciones Multimedia, Gandia, Spain"],"affiliations":[{"raw_affiliation_string":"Universidad Polit\u00e9cnica de Valencia, Instituto de Telecomunicaciones y Aplicaciones Multimedia, Gandia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075525477","display_name":"Mar\u00eda Jos\u00e9 Canet","orcid":"https://orcid.org/0000-0002-6765-9219"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"M. J. Canet","raw_affiliation_strings":["Universidad Polit\u00e9cnica de Valencia, Instituto de Telecomunicaciones y Aplicaciones Multimedia, Gandia, Spain"],"affiliations":[{"raw_affiliation_string":"Universidad Polit\u00e9cnica de Valencia, Instituto de Telecomunicaciones y Aplicaciones Multimedia, Gandia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005437595","display_name":"Javier Valls","orcid":"https://orcid.org/0000-0002-9390-5022"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Valls","raw_affiliation_strings":["Universidad Polit\u00e9cnica de Valencia, Instituto de Telecomunicaciones y Aplicaciones Multimedia, Gandia, Spain"],"affiliations":[{"raw_affiliation_string":"Universidad Polit\u00e9cnica de Valencia, Instituto de Telecomunicaciones y Aplicaciones Multimedia, Gandia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025809855","display_name":"Pramod Kumar Meher","orcid":"https://orcid.org/0000-0003-0992-1159"},"institutions":[{"id":"https://openalex.org/I3005327000","display_name":"Institute for Infocomm Research","ror":"https://ror.org/053rfa017","country_code":"SG","type":"facility","lineage":["https://openalex.org/I115228651","https://openalex.org/I3005327000","https://openalex.org/I91275662"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"P. K. Meher","raw_affiliation_strings":["Department of Embedded Systems, Institute for Infocomm Research, Singapore"],"affiliations":[{"raw_affiliation_string":"Department of Embedded Systems, Institute for Infocomm Research, Singapore","institution_ids":["https://openalex.org/I3005327000"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5088891897"],"corresponding_institution_ids":["https://openalex.org/I60053951"],"apc_list":null,"apc_paid":null,"fwci":1.2827,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.84744212,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"20","issue":"3","first_page":"568","last_page":"573"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11797","display_name":"graph theory and CDMA systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.7736901044845581},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7072898149490356},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.609649658203125},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6027507185935974},{"id":"https://openalex.org/keywords/interpolation","display_name":"Interpolation (computer graphics)","score":0.521259605884552},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5144439339637756},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4945621192455292},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.47780710458755493},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43808430433273315},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4153721332550049},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3569602966308594},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1805054247379303},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.1346924901008606},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11470979452133179},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.07522502541542053},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07450565695762634}],"concepts":[{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.7736901044845581},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7072898149490356},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.609649658203125},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6027507185935974},{"id":"https://openalex.org/C137800194","wikidata":"https://www.wikidata.org/wiki/Q11713455","display_name":"Interpolation (computer graphics)","level":3,"score":0.521259605884552},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5144439339637756},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4945621192455292},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.47780710458755493},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43808430433273315},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4153721332550049},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3569602966308594},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1805054247379303},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.1346924901008606},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11470979452133179},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.07522502541542053},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07450565695762634},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2010.2103961","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2103961","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:riunet.upv.es:10251/35462","is_oa":true,"landing_page_url":"http://hdl.handle.net/10251/35462","pdf_url":null,"source":{"id":"https://openalex.org/S4306401500","display_name":"RiuNet (Politechnical University of Valencia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I60053951","host_organization_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","host_organization_lineage":["https://openalex.org/I60053951"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:riunet.upv.es:10251/35462","is_oa":true,"landing_page_url":"http://hdl.handle.net/10251/35462","pdf_url":null,"source":{"id":"https://openalex.org/S4306401500","display_name":"RiuNet (Politechnical University of Valencia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I60053951","host_organization_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","host_organization_lineage":["https://openalex.org/I60053951"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W58580312","https://openalex.org/W1969798173","https://openalex.org/W2013392609","https://openalex.org/W2100852839","https://openalex.org/W2101591926","https://openalex.org/W2103224479","https://openalex.org/W2107310839","https://openalex.org/W2112284020","https://openalex.org/W2128381517","https://openalex.org/W2134791857","https://openalex.org/W2143986363","https://openalex.org/W2147612369","https://openalex.org/W2162822404","https://openalex.org/W2166254972"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W3203142394","https://openalex.org/W2373535795","https://openalex.org/W2082487009","https://openalex.org/W2161474341","https://openalex.org/W2406926880"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3,25,45,79,139],"high-throughput":[4],"interpolator":[5,114,137],"architecture":[6,81],"for":[7,63,124],"soft-decision":[8],"decoding":[9,19],"of":[10,28,37,50,54,67,87,94,100,119,147],"Reed-Solomon":[11],"(RS)":[12],"codes":[13],"based":[14],"on":[15,70],"low-complexity":[16],"chase":[17],"(LCC)":[18],"is":[20],"presented.":[21],"We":[22,132],"have":[23,77,133],"formulated":[24],"modified":[26,73],"form":[27],"the":[29,51,55,59,65,71,84,88,112,117,120,135],"Nielson's":[30,74],"interpolation":[31,61],"algorithm,":[32],"using":[33,111,149],"some":[34],"typical":[35],"features":[36],"LCC":[38,90,108],"decoding.":[39],"The":[40],"proposed":[41,72,113,136],"algorithm":[42,75],"works":[43],"with":[44,128],"different":[46],"scheduling,":[47],"takes":[48],"care":[49],"limited":[52],"growth":[53],"polynomials,":[56],"and":[57],"shares":[58],"common":[60],"points,":[62],"reducing":[64],"latency":[66,86],"interpolation.":[68],"Based":[69],"we":[76],"derived":[78],"low-latency":[80],"to":[82],"reduce":[83],"overall":[85],"whole":[89],"decoder.":[91],"An":[92],"efficiency":[93],"at":[95],"least":[96],"39%,":[97],"in":[98,138],"terms":[99],"area-delay":[101],"product,":[102],"has":[103],"been":[104],"achieved":[105],"by":[106,110],"an":[107,125],"decoder,":[109],"architecture,":[115],"over":[116],"best":[118],"previously":[121],"reported":[122],"architectures":[123],"RS(255,239)":[126],"code":[127],"eight":[129],"test":[130],"vectors.":[131],"implemented":[134],"Virtex-II":[140],"FPGA":[141],"device,":[142],"which":[143],"provides":[144],"914":[145],"Mb/s":[146],"throughput":[148],"806":[150],"slices.":[151]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
